Achieving negative Vgs in FET VCO by moving Rd to source pin. Any potential problems?

My question briefly:
New schematic is the same as combo-bias on this picture (most-right picture)

My Rs is around 40 Ohm
On this schematic, if current Ids becomes more negative with more negative Vgs (till some point), does not it lead to larger Igs which again result in more negative Vgs? As Vgs will depend on Igs and vice versa, would not it make impossible to achieve some biasing points, because biasing will be always tend to settle near maximum Igs?


My question details:
I just finished prototype testing of my new VCO. Now I want to remove negative voltage supply.
I use very simple biasing scheme, using single resistor Rdrain, Vcc=5v.
Drain pin: Single resistor Rdrain determines load curve, Rdrain is connected between drain pin and 5v supply. Voltage drop across Rdrain as around 1..1.5v
Source pin: source is connected to ground through high impedance biasing line
Gate pin: is biased at 0...-1v through high impedance biasing line.
Frequency of oscillation is determined by biasing: F=f(Vgs)

Now I want to connect Rdrain between ground and source pin, so Vg becomes negative relative to Vs without using negative voltage supply. Then applying 0..+1v biasing voltage to Vg will achieve the same effect as applying -1v..0v in initial setup. The problem is that voltage drop across resistor depends on Vgs voltage:
1) if I make Vgs more negative by some amount , current through FET is increased
2) as current is increased, voltage drop U=R*I is increased too, leading to even more negative Vgs:

In initial setup source pin was directly connected to ground and Vs did not depend on Vgs.
In new setup source voltage is lifted above the ground using resistor.
F=f( Vgs( I( Vgs(...) ) ) ). Will it settle at some biasing point, or such biasing scheme is a bad idea? Would not it self-bias itself to some point near -0.8v instead of biasing at say -0.2v, and also make bias oscillate around -0.8v with some low khz...mhz range frequency?

It's not actually clear how the biasing problem is related to VCO design, would be clearer if you show the real VCO circuit.

Source resistor tends to stabilize the drain current, without a specification of intended Id range, we can't suggest a suitable circuit. Of course you can derive the feasible Id range of a particular circuit yourself by putting in the FET Id(Vgs) characteristic.

Single supply operation with large Id range might be easier to achieve if you tie the gate to ground and feed the control signal to the drain node.

Source degeneration kills stage gain. Propping the
source up on top of a good low noise diode could
be somewhat better. If you need stage gain, which
you'd have to decide for yourself.

Or you could select a FET:drive combo with a more
fortunate VT and/or control voltage swing.

Hi,

These pdfs are about JFET biasing methods, if you haven't seen them maybe something will be of use.

This one is (old) and about a micro-power regulator, but it has a JFET biased off a single supply too, so maybe the method is of interest to you or someone else.
View attachment A Novel JFET Micro-Power Voltage Regulator AN-6612.pdf.pdf

By the by, I'd like to see an IC that is an inverting charge pump and LDO-style voltage regulator in one package to address the hateful variation in VGS(off) of JFETS. Just imagine: no checking for some obscure VGS(off) you need ever again or using great but imperfect biasing systems that leave a lot to be desired where some notion of precision is a requirement, i.e. those that appear in the pdfs.

Thank for your answers. I decided to make few prototypes and give it a try.

I have additional question. In my design radial stubs connected to both source pins of FET to provide virtual ground at 2*F0.
So each source pin have radial stub on it. At the same time FET spice model provides only single source pin (renesas FETs).
How to connect two radial stubs in simulator schematic then, should I simply connect them in parallel to a single source pin?

You should look at the FET model to see if it embodies
inductances.

If it doesn't then maybe you are "trying too hard" re the
stubs (tline model?).

dick_freebird said:

You should look at the FET model to see if it embodies
inductances.

If it doesn't then maybe you are "trying too hard" re the
stubs (tline model?).

Click to expand...

I understand that, and experienced gain problems with LNA, when vias was to big and too far from source pin. In this particular case I do not worry about source resistor too much. I use source radial stubs to make RF ground at 12 GHz, it stabilizes my transistor from 6 to 18GHz, and provides negative resistance around 5GHz. My recent prototype showed 4GHz and mode jump to 6GHz, which was predicted by calculations. I fixed that already, hopefully new prototype will be much better.