+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Full Member level 4
    Points: 1,772, Level: 9

    Join Date
    May 2014
    Posts
    215
    Helped
    21 / 21
    Points
    1,772
    Level
    9

    Support or lack thereof for sv trireg & recommened alternatives?

    I've inherited some system verilog code. Within the code it has the following

    Code SystemVerilog - [expand]
    1
    2
    
    trireg sd_cmd
    assign sd_cmd = sd_cmd_oe ? cmdIn : 1'bz;
    Vivado Xsim has thrown a wobbly and has reported this.
    XSIM 43-4096 - Trireg is not supported.

    So, my questions are simply this.
    1. Couldn't I simply have a register
    2. What is the point of trireg?

    Regards,

    •   Alt3rd January 2018, 13:39

      advertising

        
       

  2. #2
    Advanced Member level 5
    Points: 35,867, Level: 46
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,563
    Helped
    1913 / 1913
    Points
    35,867
    Level
    46

    Re: Support or lack thereof for sv trireg & recommened alternatives?

    Ive never seen one before. From googling, trireg was meant to be used for modelling capacitive networks. If it's in some code for an FPGA - sack the coder. If all the drivers are 1'bz, then it retains whatever the last value was (other than Z).

    This is obviously someone thinking trireg means "tri-state register". Incorrect. This can be modelled with a simple reg or logic type.
    In SV, variable types are far more inter-changable. Just ignore silly things like trireg and any analogue modelling stuff.



    •   Alt3rd January 2018, 14:26

      advertising

        
       

  3. #3
    Super Moderator
    Points: 241,334, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    41,891
    Helped
    12754 / 12754
    Points
    241,334
    Level
    100

    Re: Support or lack thereof for sv trireg & recommened alternatives?

    FPGAs have no internal tristate nodes. Assigning high Z makes only sense for bidirectional inout ports. There's no need of using trireg for it.



    •   Alt3rd January 2018, 14:34

      advertising

        
       

  4. #4
    Advanced Member level 4
    Points: 7,314, Level: 20
    Achievements:
    7 years registered Created Blog entry
    dpaul's Avatar
    Join Date
    Jan 2008
    Location
    Germay
    Posts
    1,076
    Helped
    238 / 238
    Points
    7,314
    Level
    20
    Blog Entries
    1

    Re: Support or lack thereof for sv trireg & recommened alternatives?

    See this link - http://www.asic-world.com/verilog/syntax3.html and the section 'Types of Nets'.

    Have never come come across trireg!

    XSIM 43-4096 - Trireg is not supported.
    Xilinx also maintains a list of non-supported constructs.
    Last edited by dpaul; 3rd January 2018 at 14:52.
    .....yes, I do this for fun!



--[[ ]]--