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[SOLVED] Support or lack thereof for sv trireg & recommened alternatives?

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I've inherited some system verilog code. Within the code it has the following

Code SystemVerilog - [expand]
1
2

trireg sd_cmd
assign sd_cmd = sd_cmd_oe ? cmdIn : 1'bz;

Vivado Xsim has thrown a wobbly and has reported this.
XSIM 43-4096 - Trireg is not supported.

So, my questions are simply this.
1. Couldn't I simply have a register
2. What is the point of trireg?

Regards,
 

Ive never seen one before. From googling, trireg was meant to be used for modelling capacitive networks. If it's in some code for an FPGA - sack the coder. If all the drivers are 1'bz, then it retains whatever the last value was (other than Z).

This is obviously someone thinking trireg means "tri-state register". Incorrect. This can be modelled with a simple reg or logic type.
In SV, variable types are far more inter-changable. Just ignore silly things like trireg and any analogue modelling stuff.
 

FPGAs have no internal tristate nodes. Assigning high Z makes only sense for bidirectional inout ports. There's no need of using trireg for it.
 

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