Where is the pwell in the deep nwell

Fig.1 is the deep nwell nmos layout generated from the schematic. The out box line shows that they are two layers overlapped, dnw and wellbody.

In Fig.2, I add a ptap to the bulk, short S node and bulk. I add a ntap ring inside the deep well box, which makes the nwell connected to vdd.

Questions:
1. Is it correct that I add the ntap ring inside the deep nwell to connected nwell with vdd as shown in the Fig.2?

2. It seem that the bulk(pwell) in Fig.2 can't be related to pwell in Fig.4. Bulk(pwell) in Fig.2 is just a tiny part which is around source node. While the pwell in Fig.4 are all round the source and drain node. Is Fig.2 layout is coresponded that the Fig.4 layout?

3. If I add the bulk around the transistor in Fig.4, and add ptap to the bulk, does the pwell from Fig.4 now can coresponed to that from Fig.4?

4. If I use the bulk(pwell) drawing method in Fig.2, is it correct?

Thanks.

shanmei said:

Questions:
1. Is it correct that I add the ntap ring inside the deep nwell to connected nwell with vdd as shown in the Fig.2?

Click to expand...

Yes.

shanmei said:

2. It seem that the bulk(pwell) in Fig.2 can't be related to pwell in Fig.4. Bulk(pwell) in Fig.2 is just a tiny part which is around source node. While the pwell in Fig.4 are all round the source and drain node. Is Fig.2 layout is coresponded that the Fig.4 layout?

Click to expand...

No.

shanmei said:

3. If I add the bulk around the transistor in Fig.4, and add ptap to the bulk, does the pwell from Fig.4 now can coresponed to that from Fig.3?

Click to expand...

Yes.

shanmei said:

4. If I use the bulk(pwell) drawing method in Fig.2, is it correct?

Click to expand...

Fig.2: no ; Fig.3: yes (same question as #3).

Now I understand that we should add the ptap around the nmos devices for analog circuit layout. Adding ntap around the pmos devices as well. Thanks, Erikl.

Yes,you must have concept that mos devices are 4 terminal devices! Sometimes may exsit 5 terminal!