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Deep N well transistor, How can I know

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simplsoft

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Hello

I want to use bulks of the NMOS transistor. I have read about the deep N well that transistor should be in deep N well. How ca I know that transistors are in deep well. Is it better to biased the bulks of Nmos or Pmos. I have read that PMOS is better if their bulk are to be driven. Whats the purpose of using bulk driven PMOS not NMOS?
 

In any vanilla CMOS process on p-substrate you can install N-wells where you need them, so PMOS may have their private N-well bulk where necessary. This isn't possible for NMOS in p-substrate.

Should you need bulk-controllable NMOS, you need a more expensive double- or triple-well process, which can build P-wells in N-wells: triple-well.png
 
In schematic views all you have to go by is the naming
of the master, which is tied to its construction (see the
PDK / device application docs).

In layout views, by inspection - there will be a DNW layer
and for PCells, likely a text that should correspond to the
schematic instance master name.

It's not that NMOS don't benefit from a drivable bulk node,
but that low cost CMOS doesn't provide a separate bulk
connection - rather, a global psub! (P epi and P+ handle,
or actual P bulk uniform silicon in the cheapest cases).
The intervening deep NWell accommodates a less-deep
PWell to house NMOS with Pbody freedom, allow high side
HV MOS / LDMOS and so on.
 

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