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    Power Vs Area utilization in an FPGA

    I am working on area optimization of Image coders in FPGAs. I have modified an existing design, consuming more area into one that utilizes less area (functionality remains same). I want to ask if small area utilization mean also low power consumption? Also what should be my approach if I want to optimize power efficiency of my architecture, which is quite large as compared to signal processing applications.

    •   Alt28th December 2017, 06:26

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    Re: Power Vs Area utilization in an FPGA

    It can depend. Lower area doesn't sound like a bad start. That said, you should read any power optimization guides for your FPGA. IIRC, the biggest example was not setting the enable for BRAM when you aren't using it. In some designs, the extra read is safe and there is a little less area to avoid generating a clock enable that doesn't affect logic. But the extra enables lead to increased power consumption apparently. There are also guides for different bram modes and how each affects power.

    You would also need to know if there are issues with IO power.



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    Re: Power Vs Area utilization in an FPGA

    Can you suggest me the best pdf for power consumption, that I can go through?



    •   Alt28th December 2017, 07:04

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    Comparison of area utilization among various FPGAs

    I have to compare my work to previous works done by other people. I am using Zedboard, they have used other boards. Some of the boards they have used are Virtex 6, Virtex 5, Virtex 2000E and Virtex II. I have to compare area utilization. How can I do so, as the platforms seem to be different? Although, I have seen a paper comparing on the basis of logic cells.



    •   Alt30th December 2017, 11:12

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    Re: Power Vs Area utilization in an FPGA

    Comparing resource utilisation to older technologies isnt really very helpful. The Luts are different between generations from a 4 input lut on the Virtex II to 6 input luts on the 7 series. So 1 Lut on the zedboard might (and stress might) be doing the same job as several luts on the Virtex II. The only way to compare is to take identical code on both and check the resource usage and FMax.

    Newer technology should always be faster and use less power than older generations.

    Also, when checking for power, unless you are using a significant % of the chip, a difference of a few registers here and there is going to make very little difference to the power usage. FPGAs are power hungry devices, and power use is really based on switching. So a faster clock is likely to consume more power.



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    Re: Power Vs Area utilization in an FPGA

    But in case two boards have same technology(for example virtex 6, and zedboard use 6-input LUTs). Can we compare at least these two for resources? (Not speed or power).
    In general is there any parameter on the basis of which different designs on different technologies can be compared? I have come across some papers, which compare on the basis of logic cells, normalized throughput etc. Is this a good approach? Or is there a better approach than this?



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    Re: Power Vs Area utilization in an FPGA

    To Me, the most important way to compare two different implementations is : "Does it meet my design goal"
    If I need a design that needs to perform Fn with a throughput of XGB/s, then as long as it meets those goals, I dont really care how it does it. If I have a choice of two, I will then look at secondary considerations, mainly how portable it is. Is the code well written, easy to modify and port to a new design. If the really "good" design is inflexable and not very portable, and poorly documented, that may mean I use a 2nd option as it may be easier to modify an fix later.

    Simply comparing two designs based on area or speed is not that important to me. The most important is whether the code is well written, well commented, well documented and does it meet the design specifications.



    •   Alt30th December 2017, 12:52

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    Re: Power Vs Area utilization in an FPGA

    as long as it meets those goals, I dont really care
    I agree with you...but
    From research point of view, if an architecture is already reported to be inefficient, as it consumes more area or provides low throughput (for example). You suggest a fix, then you definitely have to compare area vs area and throughput vs throughput. If there is some trade-off, you have to mention it.



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    Re: Power Vs Area utilization in an FPGA

    Probably, but these kind of comparisons are fairly meaningless in the real world, and probably why Ive never really seen any research on FPGAs from a university that ive taken seriously. The code that goes with it is usually pretty poor too. White papers from other industry sources are usually more useful and more relevant.
    By all means, compare areas or throughput if you like. I dont really see where this thread is going. Unless your design fits exactly into someone elses problem, they will probably write their own version anyway.


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