NichollsGlen
Newbie level 2
Hello everyone,
I have designed a simple QPSK modulator and there are a few issues with my design that I am not sure how to fix, partly due to how I designed my DDS. I designed the modulator in two ways, the first using rotation flags based on whether the even/odd bit is 0/1 and the second method is using a for loop to xor the LUT values with the even/odd bits. I came to both of these methods from BPSK modulator I designed beforehand that worked perfectly. However, the first issue is that I have two seperate clk domains, one for the DDS and the other for the data as my digital sin/cos wave would just look garbled if I didn't do this. My biggest issue, though, is that when I sum the I and Q legs from the DDS for the IQ merge, the output signal looks like there are overflows when they are in phase, (my I/Q and IQ_merge are unsigned and I am looking at the tb using signed analog view) but the maximum value in the LUT is 8192 with 14 bits of resolution. Here are my two questions:
1. Is it best to scrap these approaches and design the DDS/CORDIC to receive the desired phase based on the even/odd IQ map?
2. How can I tie everything together so that the data generation and the DDS are in the same clock domain?
If my questions are not clear, I can attach some screenshots and my vhdl code.
I have designed a simple QPSK modulator and there are a few issues with my design that I am not sure how to fix, partly due to how I designed my DDS. I designed the modulator in two ways, the first using rotation flags based on whether the even/odd bit is 0/1 and the second method is using a for loop to xor the LUT values with the even/odd bits. I came to both of these methods from BPSK modulator I designed beforehand that worked perfectly. However, the first issue is that I have two seperate clk domains, one for the DDS and the other for the data as my digital sin/cos wave would just look garbled if I didn't do this. My biggest issue, though, is that when I sum the I and Q legs from the DDS for the IQ merge, the output signal looks like there are overflows when they are in phase, (my I/Q and IQ_merge are unsigned and I am looking at the tb using signed analog view) but the maximum value in the LUT is 8192 with 14 bits of resolution. Here are my two questions:
1. Is it best to scrap these approaches and design the DDS/CORDIC to receive the desired phase based on the even/odd IQ map?
2. How can I tie everything together so that the data generation and the DDS are in the same clock domain?
If my questions are not clear, I can attach some screenshots and my vhdl code.