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  1. #1
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    Technology-based wire delay scale factors

    Hi all!
    During CTS stage in Synopsys ICC I observed the .log file and found some information about technology-based delay scale factors (see .log below):

    Technology-based gate delay scale factors (normalized to the highest):
    Corner ':max': 1.000
    Corner 'WL:min': 1.000
    Corner 'TEST_TY:max': 0.644
    Corner 'TEST_ML:max': 0.457
    Corner 'TEST_BC:max': 0.450
    Corner 'T1:max': 0.551
    Corner 'ML:max': 0.457
    Corner 'BC:max': 0.450
    Corner 'WC:max': 0.865
    Technology-based wire delay scale factors (normalized to the highest):
    Corner ':max': 1.000
    Corner 'WL:min': 1.000
    Corner 'TEST_TY:max': 1.000
    Corner 'TEST_ML:max': 1.000
    Corner 'TEST_BC:max': 1.000
    Corner 'T1:max': 1.000
    Corner 'ML:max': 1.000
    Corner 'BC:max': 1.000
    Corner 'WC:max': 1.000
    Using the following scale factors for float pins:
    Corner ':max': 1.000
    Corner 'WL:min': 1.000
    Corner 'TEST_TY:max': 0.716
    Corner 'TEST_ML:max': 0.566
    Corner 'TEST_BC:max': 0.560
    Corner 'T1:max': 0.641
    Corner 'ML:max': 0.566
    Corner 'BC:max': 0.560
    Corner 'WC:max': 0.892
    Worst clock corner: :max
    Worst RC delay corner: :max
    Using normal effort optimization


    I use all necessary technology files for CTS (i.e. TLU+, etc), and the main question is why wire-delay scale factor is constant (1.0)? Why it cannot changes like, for example, logical gates?

    •   Alt26th December 2017, 12:07

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  2. #2
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    Re: Technology-based wire delay scale factors

    It does change, there are process corners for wires just like for logic: best, typical, worst, etc. In Cadence environment this comes from the qrc files, not sure what is the equivalent in synopsys world.
    Really, I am not Sam.



    •   Alt26th December 2017, 21:46

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  3. #3
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    Re: Technology-based wire delay scale factors

    Thank you for your answer!
    Yes, I understand, that it does. But what the reason that ICC reports Technology-based wire delay scale factors equal for all corners? How I can determine what exact delay scale factor fol wires for specific corner?



    •   Alt27th December 2017, 16:16

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    Re: Technology-based wire delay scale factors

    Quote Originally Posted by ua6bqg View Post
    Thank you for your answer!
    Yes, I understand, that it does. But what the reason that ICC reports Technology-based wire delay scale factors equal for all corners? How I can determine what exact delay scale factor fol wires for specific corner?
    Maybe you didn't provide the tool with the right files.
    Really, I am not Sam.



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    Re: Technology-based wire delay scale factors

    I have provided TLU+, tf, mw_lib, .db files for macro and cells....sdc file....what else?



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    Re: Technology-based wire delay scale factors

    Quote Originally Posted by ua6bqg View Post
    I have provided TLU+, tf, mw_lib, .db files for macro and cells....sdc file....what else?
    Hard to say. I am not a heavy Synopsys user. What I can say for sure is that wire scale factor tables are not so popular with modern technologies as they are not accurate enough. However, the tools still support it. In my most recent tapeout I had all my tables as 100/100/100 whereas extraction would actually do the job of calculating pessimistic/optimistic Rs and Cs for wires.
    Really, I am not Sam.


    1 members found this post helpful.

    •   Alt27th December 2017, 19:09

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    Re: Technology-based wire delay scale factors

    Quote Originally Posted by ThisIsNotSam View Post
    ... In Cadence environment this comes from the qrc files, not sure what is the equivalent in synopsys world.
    In Synopsys world (StarRC world), a direct analog of QRC techfiles are ITF files (source files - text files (encrypted or not) defining BEOL stack - metal and dielectric thicknesses, dielectric constants, resistivities, manufacturing effects, etc.), and NXTGRD files (binary databases created from ITF files, for various metal lines patterns, for capacitance extraction). StarRC-generated SPF file contains a pointer to NXTGRD file used for extraction.



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