entrepreneer
Newbie level 3
Is there a methodology to determine based on process node which functions should be paralell or ran in sequence when starting initial design? Difference I am focussing on is from 16nm to 10nm/7nm.
Just some guidance as far as how to go about that type of analysis. I did some searches this evening and will continue, but I would like to get acquianted with the forum as well.
Thinking out loud, I know there has to be timing differences between different process nodes and that would dictate the high level design. There will also probably be some chip utilization benefits (dark silicon) by leaving some parts serial and some parallel if I have the choice. Just wanted to know if there was a methodology to this that was widely accepted.
Just some guidance as far as how to go about that type of analysis. I did some searches this evening and will continue, but I would like to get acquianted with the forum as well.
Thinking out loud, I know there has to be timing differences between different process nodes and that would dictate the high level design. There will also probably be some chip utilization benefits (dark silicon) by leaving some parts serial and some parallel if I have the choice. Just wanted to know if there was a methodology to this that was widely accepted.
