LearningSoMuch
Newbie level 2
How would I replicate this VHDL process into Verilog?
then inputa, input b, and outputa is
a is input std_logic
b is variable b : unsigned(0 downto 0);
Code:
begin
inputa <= (others => '-');
inputb <= (others => '-');
outputa <= "-";
if a = '1' then b := "1"; else b := "0"; end if;
Code:
signal inputa, inputb, outputa : unsigned(31 downto 0);
b is variable b : unsigned(0 downto 0);