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Vivado debugging and keep attribute!

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Vivado debuging and keep attribute!

Hi,

It was so easy for me to use ChipScope for debugging, but in vivado I've problems?

naming signals in code and finding them on vivado debugger is not easy.
in debugging by vivado, names of signals changes and it is not easy to clarify the signals I connected in to probes.
also probes bits are not named on debugger in a sequence to rename them to my signals name.

I can use Keep attribute in vhdl code to preserve signal name and so in vivado debugger I can find the signal.
but this causes Timing effects on my design.

have anybody other method for finding signals in vivado debugger in an easy way?
 

Re: Vivado debuging and keep attribute!

Why are you debuigging in chip scope? most issues should be found in simulation.
When you said the keep attribute affects timing - have you got timing specs and its now failing timing? or the use of keep changes some timing in the design you rely on to behave correctly? (this is very poor practice)
Is the design fully synchronous?

Can you post the code?
 

Re: Vivado debuging and keep attribute!

Use the attribute mark_debug with true to have Vivado automatically populate the debug core insertion tool with signals of interest.

The timing problem you have is likely due to attempts to debug combinational logic. The question is why are you coding large combo circuits in the first place? You should be designing heavily pipelined designs if there are problems meeting timing
 

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