[Moved]: Clock from Aurora protocol for asynchronous FIFO

Hi everyone,

In the FIFO of IP core, I see that the read clock and write clock of asynchronous FIFO should be free-running to ensure it work correctly.

In my project, I used the Aurora Protocol 2 lanes with (lane 1: X0Y3_GTP0 and lane 2: X0Y4_GTP1) with GT REFCLK is 60 MHz.

In the aurora_module_i.v, I see that there are REFCLKOUT_OUT and REFCLKOUT_OUT_LANE1 and then I use output of REFCLKOUT_OUT as input of DCM_ADV to generate the clock for system. Then output of DCM_ADV is go to the PLL IP core to generate the different frequency clock for WR_CLK of asynchronous FIFO.

Otherwise, I use the USER_CLK (120 MHz) from the Aurora IP core for the RD_CLOCK of asynchronous FIFO. Because I see in the Aurora documents, USER_CLK is parallel clock shared by the Aurora 8B/10B core and the user application.

I would like to ask:

1.Is the way I use to generate the WR_CLK and RD_CLK for asynchronous FIFO correct or not ?

2. Does the clock I generate in this way is free running or not free running ? Are there another way to generate good or free running RD_CLK and WR_CLK for asynchronous FIFO ?

Thank you so much.

I have no idea to give you an answer.
But there is comment about your information.
1, give the diagram instead of long description using texts.
2, I guess your problem is in FPGA job, but this is ASIC thread.