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Of course.No Synth tools support ieee.math_real for synthesisable constructs.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity rom_test is port ( clk : in std_logic; addr : in std_logic_vector(7 downto 0); data : out std_logic_vector(7 downto 0) ); end entity rom_test; architecture rtl of rom_test is type rom_t is array(0 to 255) of std_logic_vector(7 downto 0); function set_rom return rom_t is variable ret : rom_t; begin for i in ret'range loop ret(i) := std_logic_vector( to_unsigned( Integer( 256.0*sin(real(i)*MATH_PI/256.0)), 8 ) ); end loop; return ret; end function set_rom; constant rom_val : rom_t := set_rom; begin process(clk) begin if rising_edge(clk) then data <= rom_val( to_integer( unsigned(addr) ) ); end if; end process; end architecture rtl;