Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Clock to Q (Flip Flop) delay mismatches between analog and digital simulators

Status
Not open for further replies.

NikosTS

Advanced Member level 4
Joined
Jan 30, 2017
Messages
119
Helped
1
Reputation
2
Reaction score
2
Trophy points
18
Activity points
1,054
Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

Hello everyone,

I have a problem when simulating a single DFF, regarding the clock to Q( FF's output) delay.
When importing an instance of a DFF on Cadence Virtuoso and use transient analysis with a testebench that simply produces pulses as an input to the flip flop, I get around 140 ps of delay between the clock's rising edge and the change at the outpin pin ( Q ).
On the other hand, when i synthesize a DFF on Cadence RTL Compiler and then use NCLaunch to simulate it ( annotating the .sdf file produced by RTL Compiler ) I get a delay of 232 ps.

The same cell i use as an instance on Virtuoso is also produced from the synthesis procedure. Also, the operating conditions are typical on both cases.

Anyone has any idea as to why this would happen?
If i didnt make something clear, please tell me.

Thank you in advance,
Nikos
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

are you using the same load for both simulations?
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

Hello,
I have not specified anything about load for the simulations. As long as at both cases the same flip flop is realised, the load shouldnt be the same?
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

Digital simulations will embed some worst casing (not
to say, the worst possible case you could create -
but at some point some digital library developer said
what the corner temp, supply, process, wireload /
fanout load coverage would be for design closure
purposes).

Analog simulations instead use either nil or extracted
parasitics from a schematic or layout based view. And
the PVT conditions are whatever you asserted.

There is some corner case where analog and digital
match. Hopefully this is worse than where you get
to live.

Check that.
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

Hi,

that simply produces pulses as an input to the flip flop
Which input? D or Clk?

I´d feed back Q_inverted to D:
D = !Q
Then every rising edge at CLK will generate a transition at Q.

Then you can measure the Clk to Q delay.

Klaus
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

@dick_freebird

I have simulated the design on analog simulator using the worst conditions ( worst corner and highest/lowest temperature ) but still the delay rise to around 190 maximum whilst on the digital simulator i get 232 as i mentioned before.

@KlausST

By input i mean the D pin (the clock pin has another pulse source connected to it ). Sure i can try the connection you mentioned, but i am pretty sure i will get almost the exact same delay which is much lower than the one the digital simulator produces.
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

Hello,
I have not specified anything about load for the simulations. As long as at both cases the same flip flop is realised, the load shouldnt be the same?

You can either guess or force the load to be the same. Same goes for process corner.
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

I set the same corner, temperature and voltage for both types of simulation.
When i set the load to a certain value ( 10 fF ), the analog simulation produces a delay of 226 ps and the digital one 232 ps which is pretty close.
If i change the value of the load to 20 fF, the analog simulation produces a delay of 303 ps this time while the digital still prduces 232 ps.
Any insight?
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

You are probably not setting the load correctly on the digital-like simulation or you are measuring at the wrong 'node'.
 

Re: Clock to Q (Flip Flop) delay missmatch between analog and digital simulators

Could you provide me some more info on how to set it properly?
On the .sdf file ( user constraint file ) i use : set_attribute external_pin_cap 'capacitance_value' 'design_output_pin' .
As far as the selection of node is concerned, the design consists of just one output node ( pin ) and i am seeing the delay from the clock to that pin.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top