sandipan
Newbie level 2
Dear All,
Currently I am doing project which involves Digital implementation of DC-DC Buck converter in 28nm CMOS technology. Supply voltage is 3.7V. As per project specification, output voltage at the load (Resistive load) should be between 0.5V - 1V between 10 micro watts and 100 micro watts. Also as per project specification , power stage of DC-DC buck converter which consists of 4 main parts (i) main switching transistors (ii) LC filter (iii) Resistive Load (iv) cascaded 4 or 5- stage drivers for both pmos & nmos swtiching transistors, all these needs to be implemented in analog circuit form (please refer attachment - dc_dc_buck_conv.PNG). Feedback loop of DC-DC buck converter should be implemented in digital domain.
Feedback loop of DC-DC buck converter is a digital controller which basically control voltage regulation in the entire circuit. This digital controller consist of 3 blocks - (i) A/D converter - interfaced with the signal across Load (ii) digital PID regulator - please see below attachment 20170518132622932_PID regulator.pdf (iii) digital PWM block which regulate duty cycle , basically acting as a DAC between digital controller and analog power stage.
I have generated VerilogA source code from Cadence modelwriter for A/D converter (see below verilog A code) but still unable to generated 8-bits digital signal at the output. I don't know how to set setpoint, which needs to be subtracted from the digitized value of the output voltage to yield the digital error value and this digitized error signal has to be fed as an input for next stage block - digital PID regulator . Also I wrote verilog code for digital PID regulator (see below 2 different source codes and attachments named - 20170518132622932_PID regulator.pdf and 20170829143117788.pdf ). I don't know which model would be appropriate for this project. Also in the last digital block i.e. DPWM block in which output of PID regulator is compared with counter output, so basically two modules - counter.v and PID_regulator.v has been instantiated. But as per another attachment (tasks needs to be done.pdf ), my project coordinator mentioned to include clock generator for counter within PWM_controller functional so that ADC and PWM_controller operate synchronously. Detailed information as suggested my supervisor mentioned in the attachment 'tasks needs to be done.pdf' . I wrote RTL for clock generator for 1000ns cycles (1MHz Switching frequency fs for DPWM block to generate duty cycle), but don't know where to include inside PWM_controller.v . Please suggest me how to approach for next steps as without proper voltage regulation in digital controller feedback loop, switching action ON & OFF for main power transistors won't work.
Appreciate your help in this context.
Best regards,
Rahul
Currently I am doing project which involves Digital implementation of DC-DC Buck converter in 28nm CMOS technology. Supply voltage is 3.7V. As per project specification, output voltage at the load (Resistive load) should be between 0.5V - 1V between 10 micro watts and 100 micro watts. Also as per project specification , power stage of DC-DC buck converter which consists of 4 main parts (i) main switching transistors (ii) LC filter (iii) Resistive Load (iv) cascaded 4 or 5- stage drivers for both pmos & nmos swtiching transistors, all these needs to be implemented in analog circuit form (please refer attachment - dc_dc_buck_conv.PNG). Feedback loop of DC-DC buck converter should be implemented in digital domain.
Feedback loop of DC-DC buck converter is a digital controller which basically control voltage regulation in the entire circuit. This digital controller consist of 3 blocks - (i) A/D converter - interfaced with the signal across Load (ii) digital PID regulator - please see below attachment 20170518132622932_PID regulator.pdf (iii) digital PWM block which regulate duty cycle , basically acting as a DAC between digital controller and analog power stage.
I have generated VerilogA source code from Cadence modelwriter for A/D converter (see below verilog A code) but still unable to generated 8-bits digital signal at the output. I don't know how to set setpoint, which needs to be subtracted from the digitized value of the output voltage to yield the digital error value and this digitized error signal has to be fed as an input for next stage block - digital PID regulator . Also I wrote verilog code for digital PID regulator (see below 2 different source codes and attachments named - 20170518132622932_PID regulator.pdf and 20170829143117788.pdf ). I don't know which model would be appropriate for this project. Also in the last digital block i.e. DPWM block in which output of PID regulator is compared with counter output, so basically two modules - counter.v and PID_regulator.v has been instantiated. But as per another attachment (tasks needs to be done.pdf ), my project coordinator mentioned to include clock generator for counter within PWM_controller functional so that ADC and PWM_controller operate synchronously. Detailed information as suggested my supervisor mentioned in the attachment 'tasks needs to be done.pdf' . I wrote RTL for clock generator for 1000ns cycles (1MHz Switching frequency fs for DPWM block to generate duty cycle), but don't know where to include inside PWM_controller.v . Please suggest me how to approach for next steps as without proper voltage regulation in digital controller feedback loop, switching action ON & OFF for main power transistors won't work.
Appreciate your help in this context.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 //Verilog HDL for "fc_logic", "PID_regulator" "functional" module PID_regulator ( output signed [7:0] u_out, // output pwm_control port input signed [7:0] e_in, // input errror from ADC input clk, // clock input input reset // Reset input ); parameter kp = 1; parameter ki = 0.001; parameter kd = 0; reg signed [7:0] u_prev; // Register to store previous values of pwm_control output reg signed [7:0] e_prev[1:2]; // Register to store prvious error bits always @ (posedge clk)begin if (reset == 1) begin u_prev <= 0; e_prev[1] <= 0; e_prev[2] <= 0; end else begin e_prev[2] <= e_prev[1]; e_prev[1] <= e_in; u_prev <= u_out; end end assign u_out = u_prev + kp*e_in - ki*e_prev[1] + kd*e_prev[2]; endmodule xxxxxxxxxxxxxxxxxxxxx......................................................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx //Verilog HDL for "fc_logic", "PID_compensator" "functional" module PID_regulator ( output signed [7:0] pwm_control_out, // output pwm_control port input signed [7:0] error_in, // input errror from ADC input clk, // clock input input reset // Reset input ); parameter kp = 1; // proportionality constant parameter ki = 0.001; // Integral constant parameter kd = 0; // Derivative constant - no dead/lag time reg signed [7:0] pwm_control_out; // Register to hold pwm control output reg signed [7:0] error_in_prev[1:2]; // Register to store prvious error bits always @ (posedge clk)begin if (reset == 1) begin error_in_prev[1] <= 0; error_in_prev[2] <= 0; error_in <= 0; pwm_control_out <= 0; end else begin error_in_prev[2] <= error_in; error_in_prev[1] <= error_in + error_in_prev[1]; end pwm_control_out <= kp*error_in + Ki*error_in_prev[1] + kd*error_in - kd*error_in_prev[2]; end endmodule ..............................................xxxxxxxxxxxxxxxxxxxxxxxxxxxxx........................................................................ // FUNCTION: Analog to Digital Converter // VERSION: $Revision: 2.13 $ // AUTHOR: Cadence Design Systems, Inc. // // GENERATED BY: Cadence Modelwriter 2.31 // ON: Sun Jun 04 11:24:00 CEST 2017 // // Description: Ideal Analog to Digital Converter // Generates an N bit ADC. // - selectable logic output levels // - model valid for negative values of vmin // - adjustable conversion time, and rise/fall time // This model is an example, provided "as is" without express or // implied warranty and with no claim as to its suitability for // any purpose. // // CCR 563324 changed voltage to electrical // // PARAMETERS: // slack = The smallest time interval considered negligible for // cross event on clock [S] // tconv = Delay from threshold crossing to output change [S] // trise = Rise time for digital output signals [S] // tfall = Fall time for digital output signals [S] // vmax = ADC Full scale output voltage [V] // vmin = ADC Zero scale output voltage [V] // vone = The voltage of a logical 1 on digital outputs [V] // vth = Threshold value of clock signal [V] // vzero = The voltage of a logical 0 on digital outputs [V] // `include "discipline.h" `include "constants.h" `define NUM_ADC_BITS 8 module a2d_conv (vin, clk, dout); input vin, clk; electrical vin, clk; output [`NUM_ADC_BITS-1:0] dout; electrical [`NUM_ADC_BITS-1:0] dout; parameter real vmax = 2; parameter real vmin = 0; parameter real one = 1.8; parameter real zero = 0.0; parameter real vth = 0.9; parameter real slack = 10p from (0:inf); parameter real trise = 10p from (0:inf); parameter real tfall = 10p from (0:inf); parameter real tconv = 1n from [0:inf); parameter integer traceflag = 0; real sample, vref, lsb, voffset; real vd[0:`NUM_ADC_BITS-1]; integer ii, binvalue; analog begin @(initial_step or initial_step("dc", "ac", "tran", "xf")) begin vref = (vmax - vmin) / 2.0; lsb = (vmax - vmin) / (1 << `NUM_ADC_BITS) ; voffset = vmin; if (traceflag) $display("%M ADC range ( %g v ) / %d bits = lsb %g volts.\n", vmax - vmin, `NUM_ADC_BITS, lsb ); generate i ( `NUM_ADC_BITS-1, 0) begin vd[i] = 0 ; end end @(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin binvalue = 0; sample = V(vin) - voffset; for ( ii = `NUM_ADC_BITS -1 ; ii>=0 ; ii = ii -1 ) begin vd[ii] = 0; if (sample > vref ) begin vd[ii] = one; sample = sample - vref; binvalue = binvalue + ( 1 << ii ); end else begin vd[ii] = zero; end sample = sample * 2.0; end if (traceflag) $strobe("%M at %g sec. digital out: %d vin: %g (d2a: %g)\n", $abstime, binvalue, V(vin), (binvalue*lsb)+voffset); end generate i ( `NUM_ADC_BITS-1, 0) begin V(dout[i]) <+ transition ( vd[i] , tconv, trise, tfall ); end end endmodule `undef NUM_ADC_BITS ...........................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx........................................................................................................................................... //Verilog HDL for "fc_logic", "PWM_Controller" "functional" //Duty cycle can be calculated as the number of clock cycles the PWM output is high / the number of clock cycles one PWM cycle requires module PWM_Controller ( e_in, // I/O Ports declared PWM_out, clk, ); input clk; //input clock port input [7:0] e_in; // 8-bit PWM input output PWM_out; // 1 bit PWM output -Duty cycle per switching cycle reg PWM_out; // internal variabe to hold PWM control output wire [7:0] counter_out; // 16 bit counter output wire [7:0] u_out; // 16-bit PID controller output-PWM codewords wire reset; // Reset input for counter always @ (posedge clk) begin if (u_out > counter_out)begin PWM_out <= 1; end else begin PWM_out <= 0; end end counter counter_inst( .clk(clk), .counter_out(counter_out), .reset(reset) ); PID_regulator PID_regulator_inst( .u_out(u_out), .e_in(e_in), .clk(clk), .reset(reset) ); endmodule ...................................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx.................................. //Verilog HDL for "fc_logic", "counter" "functional" // Implementing the sawtooth generator for PWM driver in digital hardware as 8-bit counter. module counter( clk, //clock input reset, // reset input counter_out // 8-bit output from the counter ); input clk,reset; // clock,reset- declared as an input ports output[7:0] counter_out; // counter_out declared as an 8-bit output port reg [7:0] counter_out; // internal variable to store counter_out values always @(posedge clk) begin if (reset == 1'b1)begin counter_out <= 8'b0; end else counter_out <= #1 counter_out + 1'b1; end endmodule ...............................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx...................................................................................... // clock generator module clock_gen (clk); parameter CLKPERIODE = 1000; // clock period (ns)- switching frequency fs = 1MHz i.e. 1000ns output clk; reg clk; initial clk = 0; always #(CLKPERIODE/2) clk = ~clk; endmodule
Best regards,
Rahul
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