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Digital Implementation of feedback controller for DC-DC Buck converter in 28nm CMOS

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sandipan

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Dear All,

Currently I am doing project which involves Digital implementation of DC-DC Buck converter in 28nm CMOS technology. Supply voltage is 3.7V. As per project specification, output voltage at the load (Resistive load) should be between 0.5V - 1V between 10 micro watts and 100 micro watts. Also as per project specification , power stage of DC-DC buck converter which consists of 4 main parts (i) main switching transistors (ii) LC filter (iii) Resistive Load (iv) cascaded 4 or 5- stage drivers for both pmos & nmos swtiching transistors, all these needs to be implemented in analog circuit form (please refer attachment - dc_dc_buck_conv.PNG). Feedback loop of DC-DC buck converter should be implemented in digital domain.

Feedback loop of DC-DC buck converter is a digital controller which basically control voltage regulation in the entire circuit. This digital controller consist of 3 blocks - (i) A/D converter - interfaced with the signal across Load (ii) digital PID regulator - please see below attachment 20170518132622932_PID regulator.pdf (iii) digital PWM block which regulate duty cycle , basically acting as a DAC between digital controller and analog power stage.

I have generated VerilogA source code from Cadence modelwriter for A/D converter (see below verilog A code) but still unable to generated 8-bits digital signal at the output. I don't know how to set setpoint, which needs to be subtracted from the digitized value of the output voltage to yield the digital error value and this digitized error signal has to be fed as an input for next stage block - digital PID regulator . Also I wrote verilog code for digital PID regulator (see below 2 different source codes and attachments named - 20170518132622932_PID regulator.pdf and 20170829143117788.pdf ). I don't know which model would be appropriate for this project. Also in the last digital block i.e. DPWM block in which output of PID regulator is compared with counter output, so basically two modules - counter.v and PID_regulator.v has been instantiated. But as per another attachment (tasks needs to be done.pdf ), my project coordinator mentioned to include clock generator for counter within PWM_controller functional so that ADC and PWM_controller operate synchronously. Detailed information as suggested my supervisor mentioned in the attachment 'tasks needs to be done.pdf' . I wrote RTL for clock generator for 1000ns cycles (1MHz Switching frequency fs for DPWM block to generate duty cycle), but don't know where to include inside PWM_controller.v . Please suggest me how to approach for next steps as without proper voltage regulation in digital controller feedback loop, switching action ON & OFF for main power transistors won't work.

Appreciate your help in this context.



Code Verilog - [expand]
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//Verilog HDL for "fc_logic", "PID_regulator" "functional"
 
module PID_regulator   
              (
                output signed [7:0]  u_out,        // output pwm_control port
                    input signed  [7:0]  e_in,          // input errror from ADC 
                    input clk,                               // clock input
                    input reset                            // Reset input
     
     );
     
          
              parameter kp = 1;                   
              parameter ki = 0.001;                      
              parameter kd = 0;                     
     
     
         reg signed [7:0] u_prev;              // Register to store previous values of pwm_control output
             reg signed [7:0] e_prev[1:2];      //  Register to store prvious error bits
      
        always @ (posedge clk)begin
                 if (reset == 1) begin
                     u_prev <= 0;
                     e_prev[1] <= 0;
                     e_prev[2] <= 0;
             
             end
 
                else begin
                     e_prev[2] <= e_prev[1];
                             e_prev[1] <= e_in;
                     u_prev <= u_out;
                end
        
        end
        
    assign u_out = u_prev + kp*e_in - ki*e_prev[1] + kd*e_prev[2];
    
          
endmodule
 
xxxxxxxxxxxxxxxxxxxxx......................................................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 
//Verilog HDL for "fc_logic", "PID_compensator" "functional"
 
module PID_regulator   
              (
                output signed [7:0]  pwm_control_out,       // output pwm_control port
                    input  signed [7:0]  error_in,                    // input errror from ADC 
                    input clk,                                               // clock input
                    input reset                                            // Reset input
     
     );
     
       
              parameter kp = 1;                    // proportionality constant
              parameter ki = 0.001;             //  Integral constant
              parameter kd = 0;                  //   Derivative constant - no dead/lag time
     
     
             
             reg signed [7:0] pwm_control_out;        // Register to hold pwm control output
         reg signed [7:0] error_in_prev[1:2];     //  Register to store prvious error bits
      
         always @ (posedge clk)begin
                 if (reset == 1) begin
                     error_in_prev[1] <= 0;
             error_in_prev[2] <= 0;
             error_in <= 0;
            pwm_control_out <= 0;
                     
    end
 
                else begin
               error_in_prev[2] <= error_in;
               error_in_prev[1] <= error_in + error_in_prev[1];
            end
                
        pwm_control_out <= kp*error_in + Ki*error_in_prev[1] + kd*error_in - kd*error_in_prev[2];
        
        end
        
endmodule
 
..............................................xxxxxxxxxxxxxxxxxxxxxxxxxxxxx........................................................................
 
//     FUNCTION: Analog to Digital Converter
//      VERSION: $Revision: 2.13 $
//       AUTHOR: Cadence Design Systems, Inc.
//
// GENERATED BY: Cadence Modelwriter 2.31
//           ON: Sun Jun 04 11:24:00 CEST 2017
//
// Description: Ideal Analog to Digital Converter
//   Generates an N bit ADC. 
//     - selectable logic output levels
//     - model valid for negative values of vmin
//     - adjustable conversion time, and rise/fall time
//    This model is an example, provided "as is" without express or
//    implied warranty and with no claim as to its suitability for
//    any purpose.
// 
//    CCR 563324 changed voltage to electrical
// 
// PARAMETERS:
//   slack = The smallest time interval considered negligible for
// cross event on clock [S]
//   tconv = Delay from threshold crossing to output change [S]
//   trise = Rise time for digital output signals [S]
//   tfall = Fall time for digital output signals [S]
//    vmax = ADC Full scale output voltage [V]
//    vmin = ADC Zero scale output voltage [V]
//    vone = The voltage of a logical 1 on digital outputs [V]
//     vth = Threshold value of clock signal [V]
//   vzero = The voltage of a logical 0 on digital outputs [V]
// 
 
`include  "discipline.h"
`include  "constants.h" 
`define NUM_ADC_BITS   8
 
module a2d_conv (vin, clk, dout);
 input   vin, clk;
 electrical vin, clk;
 
 output  [`NUM_ADC_BITS-1:0] dout;
 electrical [`NUM_ADC_BITS-1:0] dout;
 
  parameter real  vmax = 2;
  parameter real  vmin = 0;
  parameter real   one = 1.8;
  parameter real  zero = 0.0;
  parameter real   vth = 0.9;
  parameter real slack = 10p from (0:inf);
  parameter real trise = 10p from (0:inf);
  parameter real tfall = 10p from (0:inf);
  parameter real tconv = 1n from [0:inf);
  parameter integer traceflag = 0;
 
     real   sample, vref, lsb, voffset;
     real   vd[0:`NUM_ADC_BITS-1];
     integer ii, binvalue;
 
    analog begin
      @(initial_step or initial_step("dc", "ac", "tran", "xf"))  begin
        vref = (vmax - vmin) / 2.0;
        lsb  = (vmax - vmin) / (1 << `NUM_ADC_BITS) ;
        voffset = vmin;
            
        if (traceflag)
        $display("%M ADC  range ( %g v ) /  %d bits  = lsb %g volts.\n",
                    vmax - vmin, `NUM_ADC_BITS, lsb );
 
        generate i ( `NUM_ADC_BITS-1, 0) begin
            vd[i] = 0 ;
        end
    end
 
      @(cross ( V(clk)-vth,  1, slack, clk.potential.abstol)) begin
          binvalue = 0;
          sample = V(vin) - voffset;
          for ( ii = `NUM_ADC_BITS -1 ; ii>=0 ; ii = ii -1 ) begin
            vd[ii] = 0;
            if (sample > vref ) begin
              vd[ii] = one;
              sample = sample - vref;
              binvalue = binvalue + ( 1 << ii );
            end
            else begin
             vd[ii] = zero;
            end
            sample = sample * 2.0;
          end
          if (traceflag)
            $strobe("%M at %g sec. digital out: %d   vin: %g  (d2a: %g)\n",
                       $abstime, binvalue,  V(vin), (binvalue*lsb)+voffset);
      end
 
      generate i ( `NUM_ADC_BITS-1, 0) begin
         V(dout[i])  <+   transition ( vd[i] , tconv, trise, tfall );
      end
    end             
endmodule
 
`undef NUM_ADC_BITS
 
...........................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx...........................................................................................................................................
//Verilog HDL for "fc_logic", "PWM_Controller" "functional"
//Duty cycle can be calculated as the number of clock cycles the PWM output is high / the number of clock cycles one PWM cycle requires
 
 
 
 
module PWM_Controller ( 
 
            e_in,                     // I/O Ports declared
        PWM_out,                             
        clk,
    
    );
 
        
    input clk;                         //input clock port
    input [7:0] e_in;             // 8-bit PWM input
       
    
    output PWM_out;             // 1 bit PWM output -Duty cycle per switching cycle
    reg PWM_out;                 // internal variabe to hold PWM control output 
    
    wire [7:0] counter_out;   // 16 bit counter output
    wire [7:0] u_out;           // 16-bit PID controller output-PWM codewords
    wire reset;                   // Reset input for counter
    
    
            always @ (posedge clk)
         begin
            
            if (u_out > counter_out)begin
                PWM_out <= 1;
            end
                
            else begin
                PWM_out <= 0;
            end
            
              end
    
    
    
    counter counter_inst(
    
        .clk(clk),
        .counter_out(counter_out),
        .reset(reset)
        );
        
       PID_regulator PID_regulator_inst(
       
             .u_out(u_out),
             .e_in(e_in),
             .clk(clk),
             .reset(reset)
             ); 
 
endmodule
 
...................................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx..................................
//Verilog HDL for "fc_logic", "counter" "functional"
// Implementing the sawtooth generator for PWM driver in digital hardware as 8-bit counter.
 
 
module counter(
 
            clk,                 //clock input
        reset,             // reset input
        counter_out   // 8-bit output from the counter
 
);
 
 
 
        input clk,reset;                     // clock,reset- declared as an input ports
    output[7:0] counter_out;    // counter_out declared as an 8-bit output port
    
    reg [7:0] counter_out;     // internal variable to store counter_out values
    
    
    always @(posedge clk)
    begin
      if (reset == 1'b1)begin
         counter_out <= 8'b0;
         
      end 
      
      else 
         counter_out <= #1 counter_out + 1'b1;
    
    end
        
 
endmodule
 
...............................xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx......................................................................................
// clock generator
 
    module clock_gen (clk);
    parameter CLKPERIODE = 1000;    // clock period (ns)- switching frequency fs = 1MHz i.e. 1000ns
    output clk;
    reg clk;
 
    initial clk = 0;
 
    always #(CLKPERIODE/2) clk = ~clk;
 
endmodule


Best regards,
Rahul
 

Attachments

  • dc_dc_buck_conv.PNG
    dc_dc_buck_conv.PNG
    32.2 KB · Views: 134
  • 20170518132622932_PID regulator.pdf
    173.5 KB · Views: 143
  • tasks needs to be done.pdf
    310.7 KB · Views: 110
  • 20170829143117788.pdf
    62.7 KB · Views: 106
Last edited by a moderator:

Even the most "digital" controller will need analog sensing
of a reference quantity and an output quantity in order
to close the loop.

This could be as simple as a comparator or as complex
as a pair of ADCs with absurd precision and sample
rate. How you will deal with the data, what kind of
transient performance and DC accuracy and noise
behavior you require, all enter into your architecture
choices.

Now why you would want to do this job in 28nm
technology when the working voltage says 350nm
(sure, why not use the I/O devices of a 10X more
costly mask/wafer set?) is a serious question. As
is, the wisdom of trying to integrate power chopping
with anything like analog, RF, phase noise sensitive
or plain old noise sensitive.

I guess I'd suggest staying with the ADC problem
until you get your 8-bit word clean and properly
following the analog input quantity. Now it's pretty
certain that you could find a veriloga ADC model on
the Web (like designersguide.org, or your friend Mr.
Googlez) that works. You might need to massage
the integer to bit-field conversion at some point in
the chain, if your code isn't just all integer.
 

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