Altera Stratix 10 Hyper-Registers

In the Altera Stratix 10 they do have Hyper-Registers in the routing layer / cross-point, it seems to be a very clever way to "pipeline" much more and thereby squeeze the fmax up like x2. I could for sure use that :lol:

Are this "Hyper-Registers" technology available in any other FPGA series / Vendor?

Thx

Are this "Hyper-Registers" technology available in any other FPGA series / Vendor?

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Probably not.
But does this mean Intel's Stratix 10 will be higher performance than Xilinx's Virtex Ultrascale + ?
Same answer - probably not.

IMO, the interesting thing here is that while Intel is just starting to manufacture the 14nm Stratix 10 - Xilinx's equivalent 16nm Ultrascale + has been available for over a year...

shaiko said:

Probably not.
But does this mean Intel's Stratix 10 will be higher performance than Xilinx's Virtex Ultrascale + ?
Same answer - probably not.

IMO, the interesting thing here is that while Intel is just starting to manufacture the 14nm Stratix 10 - Xilinx's equivalent 16nm Ultrascale + has been available for over a year...

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We have had Stratix 10 parts for some time now, maybe 6 months or so, but they are from engineering lots.

https://www.prnewswire.com/news-rel...ys-first-high-end-finfet-fpgas-300211236.html
Notice the date.

What Altera / Intel need - is a software that converts Marketing Powerpoint slides to FPGA manufacturing & programming files.

ThisIsNotSam said:

We have had Stratix 10 parts for some time now

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Interesting so did you had any look into the Hyper-Registers and any experience in the benefit of this?

Reason for asking are I do work on a project where we need to have a lot of 8 bit in 8 bit out (256 bytes) s-boxes lookup stages in a pipeline core, and since the BlockRAM (ROM) M10K or M20K typical gets slow if you do not register on both in and output then you need to delay the rest of the data 64 bit = a lot of registers, and here I do see the Hyper-Registers as a very welcome solution.

So basically I'm looking for a good way top speed up s-boxes, and have been looking around to see if there were any new approach, still waiting for 8bit LUT

Design the code like you would with any other Fpga - add pipeline stages when needed in order to meet your timing requirements. The P&R Algorithm should be smart enough to map to these registers.

shaiko said:

Design the code like you would with any other Fpga - add pipeline stages when needed in order to meet your timing requirements. The P&R Algorithm should be smart enough to map to these registers.

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Sure but I will then run out of registers since I need as many pipeline core's as possible and saw the Hyper-Registers as extra resources.
There will always be a bottleneck :bang:

Why a bottleneck?
The fact that they're there gives you an added value.
Without them, your code will simply be mapped to LE/ALM registers - like it would in older Fpga generations.

There is a guide for these. It looks like there is a restriction on reset and clock enables. This could complicate design that make assumptions based on these features.

shaiko said:

Why a bottleneck?

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When you have a lot of BRAM and ALM you need more registers to load more cores into the FPGA when you get a lot of registers which gives hopefull more fmax and make you have more cores dues to loads of registers, then you need more ALM and BRAM to add even more cores.
Kind of a chicken / egg situation :thinker:

All this are sure only a problem where you need to do a lot of calculation and need to reduce the overall time or numbers of FPGA's

I like the idea of all the Hyper-Registers and I would like to see this on cheaper FPGA's as well (I do not need all the high speed transceivers)