Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[Moved]: Do EDA tools such as DC_compiler consider guardbands (timing margin) ?

Status
Not open for further replies.
J

javierh.santiago

Junior Member level 2
Joined
Dec 4, 2017
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
225
Greetings,

I am synthesizing several digital designs with "design compiler" from synopsys, and after seeing the results of timing on critical paths, I am wondering if the tool is considering time margin to avoid future violations in the critical path?

P.S. I am using Nangate 45mm Node technology.

Regards,
Francisco
 

Bottomline is there are margins everywhere, from spice to timing sign-off post fill database.

Gate level analysis is known not to be accurate enough. It is only an estimation of the actual delay that will appear after all gates are placed and routed. In this sense, yes, you can think of synthesis results as being margined.
 
Tool introduce timing margins provided by the user for modelling various behaviors which one could see in real silicon. At the DC stage we specify larger number for uncertainty to account these.We always provide the tight timing margins for the DC Tool to do a better job in optimizing the netlist.

Regards
Jaseel
 
Your silicon vendor will give you a fudge factor like 1.070458 and tell you to synthesis at a certain process corner with your nominal frequency times the fudge factor.

If you pass with 0 margin then it should work at all process corners,
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top