Help in Alliance synthesis too (SYF)

Hello,
I have designed a Finite State Machine in VHDL and I simulated the code using Modelsim and testbench, and the code works Great. I am using an open source tool called Alliance to make the synthesis and pnr etc and generate the GSD2 file by the end of this project. when I try to run the synthesis tool (SYF) this errors pop up (check the attached photo) and I don't know where do the errors come from.
I tried other FSM code written in VHDL and it worked well, so SYF works fine.
(The rest of errors come from and value assertion to the NS( next_state) signal).

Thanks in Advance.

this is the Error message




This is The Entity and architecture declaration

I tried other FSM code written in VHDL and it worked well, so SYF works fine.

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Have never used this SYF syth tool. It says syntax errors.

Where is your VHDL code? Provide us with the VHDL state machine code.
Did modelsim pass your VHDL code without errors?

dpaul said:

Have never used this SYF syth tool. It says syntax errors.

Where is your VHDL code? Provide us with the VHDL state machine code.
Did modelsim pass your VHDL code without errors?

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Yes ModelSim passed my code and simulated it correctly.
This is the top portion of Vhdl code, which the synthesis tool claims I have a syntax error in it.

could be a million things. maybe some empty character is killing the parser, some lineend not intended.

ThisIsNotSam said:

could be a million things. maybe some empty character is killing the parser, some lineend not intended.

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Yes but how comes that ModelSim didn't complain about the code and SYF is complaining (Bad Entity declaration)!

Yes but how comes that ModelSim didn't complain about the code and SYF is complaining (Bad Entity declaration)!

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As I told in #2, it would be difficult to tell without taking a look at the VHDL code.

Also understand that ModelSim & SYF are having completely different compilers. There could be many other issues.

The problem is solved by editing the test file using Notepad++ and then select all the test files then follow the instructions in the following picture.
Thanks for everyone how tried to help in anyway

Amr_Rashed said:

The problem is solved by editing the test file using Notepad++ and then select all the test files then follow the instructions in the following picture.
Thanks for everyone how tried to help in anyway

View attachment 143194

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please more details how you solved the problem
I am new user of notepad++
and I have the same error as you on SYF alliance tool

Dahlia94,

Just load the file in that notepad++ and set the file type to unix so it converts all the line ends to unix style LF only.

The file probably has mix of unix and dos type line ends. The two are not compatible and some tools (not Modelsim) may have problems with it. Note, Modelsim is cross platform so probably ignores any line end characters (probably only checks there is one). This SYF tool probably is written and run only on unix so the programmers who wrote it didnt consider the file might have a mix of both line end styles.

I find this issue with mixed line ends occurs regularly with Xilinx's built in text editor. It shows up as a ^M at the end of lines in VIM when I edit files that were edited in Xilinx's cruddy editor.