using chipscope to check signals in a design

i want to use chip scope in ISE to see some internal net of my design.
my question is from the tutorial i saw there are two paths for this.
first one is chip scope definition and connection file and the second path is IP(CORE generator and architecture wizard).
i don't know what are their differences and which one i should choose or i should use both.
can somebody help me.
thank you.

Using the coregen version means you are adding the debugging core into the design. This is done in some cases for interfaces that might have io issues -- things like DDR2 interfaces. The nets will 100% exist because they are clearly used in the design due to the core being explicitly instantiated. This flow might also be useful in built-in-self-test designs for the same reason. Basically, this approach is best if you know the nets you'll always want to debug or use for debugging ahead of time. This is rarely the case as debugging normally comes about because something doesn't work for unknown reasons.

The post-synthesis version is the one I used almost every time. There is possibly some work getting this flow into your design process, but it is worth it. The post-synthesis version allows you to select surviving nets after synthesis. This avoids the need to manually move debug signals up/down the hierarchy in code. The downside is that you might still need to ensure nets retain the correct names. Global optimization and retiming are allowed to do whatever they want. Useful nets might not exist or might have weird names or might be hard to find. For example /top/modA/modB/mySignal might actually be a signal name of "modA/modB/mySignal" in the /top module. This method also can allow you to select nets that are in different clock domains. sometimes this is still useful for debugging purposes.

To add to what vGoodtimes mentioned. You can also add attributes directly to your code to keep/preserve/noprune signals that you can't find in the post synthesis netlist.