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coding help needed in verilog

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josephine1234

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what is moving average filter? how do i get samples of a signal in verilog?
 

moving average typically refers to the FIR filter where the previous N samples are added together and then the result is multiplied by 1/N. This filter is common because a recursive implementation requires very little resources.

It should not be hard to find examples of this filter throughout the internet.

Getting samples to the filter is up to you. for simulation, you can use readmem or other file functions. For a working design you would need to interface to an ADC or something that can send the FPGA samples.
 
Hi,

What do you mean?
Are you asking about how to use an ADC?

A design usually starts with defining the task:
* input signal definition
* output signal definition

Klaus
 

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