[SOLVED] Spectre VerilogA not recognize "assign" command

gutogw said:

Hi, I don't know verilog, so I decided to generate the verilog code through RTL Compiler, then I copy and paste him in the verilogA cell view in virtuoso, but when I click to "check and extract" it shows the error below.




Warning from spectre during AHDL compile.
WARNING (VACOMP-1086):
"/home/elc138/elc138-weber/Augusto_Memory/ColumnSelecter/veriloga/veriloga.va",
line 20: `assign' is not a reserved keyword now but will be one in a future release. Parsing `assign' as an identifier for now.

Error found by spectre during AHDL compile.
ERROR (VACOMP-2259): "assign data_o<<--? [0] = data_o[7];"
"/home/elc138/elc138-weber/Augusto_Memory/ColumnSelecter/veriloga/veriloga.va",
line 20: syntax error.


This is the code. It's a simple selecter.

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Code Verilog - [expand]
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// VerilogA for Augusto_Memory, ColumnSelecter, veriloga
 
`include "constants.vams"
`include "disciplines.vams"
 
// Generated by Cadence Encounter(R) RTL Compiler RC14.27 - v14.20-s064_1
 
// Verification Directory fv/Select_4 
 
module Select_4(addr_i, write_i, data_o);
  input [3:0] addr_i;
  input write_i;
  output [127:0] data_o;
  wire [3:0] addr_i;
  wire write_i;
  wire [127:0] data_o;
  wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
  wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
  wire n_16, n_17, n_18, n_19, n_89;
  assign data_o[0] = data_o[7];
  assign data_o[1] = data_o[7];
  assign data_o[2] = data_o[7];
  assign data_o[3] = data_o[7];
  assign data_o[4] = data_o[7];
...
 
endmodule;

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