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Tri state Mosfet switch

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andrea_mori

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I need a tri state discrete MOSFET switch, to switch among +V, -V and GND.
I thought to use a couple of complementary mosfet pair as in the attached image.
Switch.JPG

In the first state 1) +5V the bottom pair is open (high impedance), while the P-Channel mosfet of the top pair is on, output is +5V.
In the second state 2) -5V the top pair is open (high impedance), while the N-Channel mosfet of the bottm pair is on, output is -5V.
In the third state 3) GND the P-Channel mosfet of the top pair and the N-channel of the bottom pair are off, while the N-Channel mosfet of the top pair and the P-channel of the bottom pair are off, output is ground.

Is that correct? Is there a problem of leakage current when one of the pair is high impedance (bottom pair when output is +5V, top pair when output is -5V)?

Thanks for your suggestions.

Andrea
 

This is a little confusing to follow, first of all there's no such part ( that I could find) as FD8958, I assume you're using the dual fdS8958. In your first circuit your bottom fet has a Vgs of 1.7 which will slightly turn it on; why? Similar problem in the second circuit where the top fet will be slightly on. In the third circuit you've got all four devices slightly on. Further, you don't have enough gate drive anywhere to turn the mosfets fully on. I think you need to rethink this
 

What kind of on resistance do you need? Because you
can do this with (say) an ADG1411 / 1412 / 1413 at
about 1.5 ohms and just need to make the state inputs
(maybe a 74HC139 and use the switch version that has
control states corresponding to the unique bit state of
the demux).

These switches purportedly work with +/-5 to +/-15V
supply and the signal range can be rail-rail (or less).
ADI is a little bit light on spec coverage when you get
away from +/-15V supplies, so maybe you see 3-5 ohms
I'd guess at 5V levels.

Your third state with all FETs off is not ground, it's open
switches and a 10K resistance -to- ground. Only with an
infinite-Z load will you see ground -potential- and in no
case will it be a decent current-return ground. Clarity.
 

Yes, the part is the FDS8958A.

It's a discrete switch for a DAC, so I need lower on resistance as possible, 100mOhm or less. Higher on resistance will affect the ladder network precision.
Since I'm using sign magnitude notation with a single ladder network, I need to switch between +V, -V and ground.

Any suggestion will be apreciated.
 

Apart from all problems of real MOSFET behavior like leakage current, charge injection etc., the circuit is basically flawed.

The GND switch is exposed to bipolar voltage, thus the bulk diode of a single 3-terminal MOSFET (bulk tied to source) starts to conduct above 0.5 V. The GND switch must be implemented as series circuit when using discrete MOSFET.
 

Using logic IC such as the 595 (usually used in discrete DAC) I have the same problem of a real MOSFET, plus I have around 13 ohm rds-on that affects the ladder precision.
That's the reason I would use discrete MOSFET switches.

Basically I need a three input/one output switch like this
Three_Way_Switch.JPG

Or I could use a single complementary MOSFET switch changing the supply rails when the signal go from positive to negative and viceversa.
Since I would use the sign magnitude notation I have two states when the signal crossing 0V (+0 and -0), so I can turn the switch to ground in both supply rails condition.
ALT_SWITCH.JPG

What is the best way?
And how to implement it?
 

I think, I already described a possible circuit in post #5. 4 transistors required, single transistor switches for +5 and -5, dual transistor in series circuit for the ground switch.

The premise of needing threefold switch for sign-magnitude isn't plausible to me, however. Why not using a regular ladder with double-throw switches after re-encoding the control word?
 

I think, I already described a possible circuit in post #5. 4 transistors required, single transistor switches for +5 and -5, dual transistor in series circuit for the ground switch.

The premise of needing threefold switch for sign-magnitude isn't plausible to me, however. Why not using a regular ladder with double-throw switches after re-encoding the control word?

With a regular R-2R DAC you have the MSB switching at zero crossing, regardless of the signal level. With a sign Magnitude DAC the MSB are not switching with lower level signals, that means lower THD and lower glitch at low level signal.
The sign magnitude DAC architecture basically is two DAC's back to back, one for the positive signal and one for the negative signal, resulting in constant distortion at all levels.

Can you post a basic schematic of the circuit described in post #5?

Thank you
 

I'm referring to a structure like below

3-fold.png

As previously mentioned, I wonder if the discrete MOSFET design can achieve reasonable performance in a regular DAC application. At least the useful speed will be very low due to charge injection.
 

I'm referring to a structure like below

View attachment 142816

As previously mentioned, I wonder if the discrete MOSFET design can achieve reasonable performance in a regular DAC application. At least the useful speed will be very low due to charge injection.

My target is a 192kHz DAC, so the latch speed is around 5uS, while Turn-on rise time and Turn-off fall time of the FDS8958A is around 10nS, so I think there is enough room.

Thanks for the basic schematic.
I understand that I can control the PMOS M4 from +5V (OFF) to 0V (ON). I also can control the NMOS M3 from -5V (OFF) to 0V (ON).
But how to control M1/M2?
If I tie M4 gate to +5V, M3 gate to -5V and M1/M2 gate to 0V, I get 0V at the output.
If I tie M4 gate to +5V, M3 gate to 0V and M1/M2 gate to +5V, I get -5V at the output.

To get +5V at the output I tie M4 gate to 0V, M3 gate to -5V, but how to control M1/M2 gate?
Simulating the circuit I get around +1V5 in all cases, M1/M2 to +5V, -5V and 0V.
 

Hi,

Could you implement this with switch/chopper JFETs, and would it make any difference to the problem? You already have a negative voltage to apply to an NFET gate. I'm thinking of the first picture in post #6, replace the switches with JFETs, an adaptation of the selectable gain around an op amp circuit, etc. I guess it would need both P and N FETs to work.
 

So far, Ctrl+/- was referenced to ground. Ctrl0 must be referenced to the source of M1/M2.
 

So far, Ctrl+/- was referenced to ground. Ctrl0 must be referenced to the source of M1/M2.

In simulation, also referencing Ctrl0 to the source of M1/M2 when I try to switch to +5V (M4 gate to 0V, M3 gate to -5V) I get around 1V5 at the output.
Seems that M1/M2 never turn off.

Also if I tie M2 gate to +5V and M1 gate to -5V I get 1.86V at the output and 928 mV at M1/M2 source. In this case NMOS M1 Vgs is around -4V and PMOS M2 Vgs is around +4V.
So I expect M1/M2 turning off.
Why they do not turn off?
 

Also if I tie M2 gate to +5V and M1 gate to -5V I get 1.86V at the output and 928 mV at M1/M2 source. In this case NMOS M1 Vgs is around -4V and PMOS M2 Vgs is around +4V.
M1 and M2 are both NMOS. Reconsider reviewing schematic.
Again, the voltage applied to Ctrl0 must be referenced to M1/M2 source. You are speaking like you are referencing it to ground.
 

Attachments

  • 5Vout.png
    5Vout.png
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Ok, I had not seen that M1 and M2 are both NMOS, now is clear and works correctly in simulation.
Now the great problem is how to control M1/M2 gates. I have 49 of these switches per channel (first 5 MSB are thermometer decoded, the remaining 18 bit are R2R decoded) and a battery of shift register to drive each switch. Each shift register controls 8 switches, so I cannot reference the power supply of a shift register to 8 different points.
I could tie M1/M2 gates to +5V when I need to switch to ground, while when I need to switch to +5V or -5V I could tie M1/M2 gates to -5V. But the shift registers does not turn from +5V to -5V, they are referenced to ground, so they turn from 0V to +5V or from 0V to -5V.

Any idea to solve the issue?
 

What issue?
Use the 0 to +5V to control M1/M2.

The issue is that I cannot reference the control of M1/M2 to their source because I use several shift registers to drive the total 98 switches, and each shift register drives 8 switches, so I have 1 reference for 8 switches, not 1 reference for 1 switch. I have to reference the control of M1/M2 to ground, to a fixed point, not to a dynamic point such as the sources of M1/M2.
That's the reason I thought to control M1/M2 using the -5V to +5V referenced to ground, but the problem is that the shift registers should output +5V when drived with "1" logic level and -5V when drived with "0" logic level.
Maybe, could I use a bjt to shift the level of the registers (from 0V to -5V)?
 

Yes, Vg of M1/M2 needs +/- 5V swing. Level shifters are obviously required. You can refer to the design of standard CMOS analog switches, they are regularly utilizing level shifter stages.

I still fear that the control signal crosstalk due to charge injection will considerably affect the achievable signal dynamic of your DAC design. I strongly suggest a rough calculation before proceeding with the design details.
 

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