What are inverting and non-inverting gates

Hello,

I would like to know more on inverting and non-inverting gates. For ex: NOT gate is inverting. How is it explained for AND OR and XOR gates.?

Thanks in advance

Hi Spoorthi_Harithas,

as the name says "Invert" means that an input HIGH level becomes a LOW level on the output and vice versa. On an AND, OR and XOR logic functions followed by an Inverter they become NAND, NOR and NXOR functions. "No-Inverting has no signal level change and is often called a buffer to drive more connected inputs.

Enjoy your design work!

Hi HTA,

Thanks for your response! I went across few books and got to know AND OR are non-inverting and XOR is neither inverting nor non-inverting. I was curious on the logic behind this though. Let me know if you can give me some insight on this?

Thanks!

The answer is really simple and almost obvious when you look at transistor level circuits.

In an inverting gate, the signal is passing an odd number of transistors so that it's overall inverted, in a non-inverting gate an even number of transistor.

In a XOR gate, the signal takes different paths, selected by the level of the other input. Thus it's neither inverting nor non-inverting.

Hi Spoorthi,

I am not sure which book you are referring but they are right. Basically in VLSI Industry we use another terminology to mention these things - Unateness.

Unateness is the property for each Timing Arc. Basically, Timing Arc is a combination of Input and output pin combination. Now as per the response, we define this property.
Like -
BUffer is Positive Unate -
Means Rising input -> Rising output or No change
Falling Input -> Falling output or No change.
In the Book sometime - it's captured as Non-Inverting.

Same you can get the point for Inverter gate.

Now, Lets talk about the AND gate.
In the 2 input AND gate - If Inputs are A & B.
When ever you make changes in A from Low to High (Means 0 to 1) - You can see that Output Either change form 0 to 1 or there will be no change in the output. This change is irrespective of value of B or change at B.
Similarly, you can see for 1->0 Transition also.
Check the Truth table, if you still has confusion.
AB Y
00 0
01 0
10 0
11 1

Like I said - for Positive Unate Timing Arc - Rising input gives Rising output or no Change. So you can see that AND gate is Non-Inverting (as per your book terminology).

Above is the direction - Now do the same mapping for Other gates and you will come to know
AND, OR, Buffer - > Non-Inverting - > Positive Unate
NAND, NOR, NOT -> Inverting -> Negative Unate
XOR, XNOR -> Neither Inverting not non-inverting - NonUnate.

You can check below article if you need more clearity.

Timing Arc
Unateness: Timing Arc

Simply speaking, inverting is .not. operator. If the result is 1, .not. 1 is zero and vice-versa. If the result is negated (apply .not. operator) the outcome will be inverted.

Consider the truth table below:

A B A.and.B A.nand.B

0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0

Some flip-flops have dual output: both Q and .not.Q are available. Basically the logic table for the inverter is

A .not.A

0 1
1 0

I hope I am cleared some confusion.

I have seen the term unateness being used a lot by logic synthesis people, but not by actual designers. Just throwing this out there. birdy123's reply summarises the question well.