Vineeth_S
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Hello All,
I have a scenario that, My High speed signals(DDR4 - Add/Cmd/Cntrol/Clk and Data, DQS) are running in a sandwich planes, above layer is solid GND (reference plane) and the below layer I have two different power planes (other than from DDR supply) and all my signals crosses split in power plane.
My stack-up have higher dielectric constant(4.x)) to the above GND reference which will increase my coupling to my signal layer, and also less dielectric constant(3.x)) to the below power plane.
--------- GND
--------- DDR4 Signals
---------PWR(two power planes, different from DDR supply)
Will this affect my DDR signals and will cause any coupling/ Integrity issue ?
Please help !
Thanks,
Vineeth Sankarakutty
I have a scenario that, My High speed signals(DDR4 - Add/Cmd/Cntrol/Clk and Data, DQS) are running in a sandwich planes, above layer is solid GND (reference plane) and the below layer I have two different power planes (other than from DDR supply) and all my signals crosses split in power plane.
My stack-up have higher dielectric constant(4.x)) to the above GND reference which will increase my coupling to my signal layer, and also less dielectric constant(3.x)) to the below power plane.
--------- GND
--------- DDR4 Signals
---------PWR(two power planes, different from DDR supply)
Will this affect my DDR signals and will cause any coupling/ Integrity issue ?
Please help !
Thanks,
Vineeth Sankarakutty