How to update flash with user logic?

I want to download bit to FLASH, not by JTAG, but by user logic. I now have one possible idea in mind:

Because CCLK is a dedicated pin, user logic cannot use it(I know by primitive it can still be used, but not now). Instead use a common-purpose IO, define it as a SPI_CLK output to FLASH.
In this method, there're actually two FPGA ports connected to the FLASH's clock port, one is the CCLK which is active during configuration, the other is SPI_CLK defined by user logic. Both CCLK and SPI_CLK are up-pulled.

The other spi related pins, such as sdi, sdo, chip_select, are multi-purpose pins which could be used later by user logic, so no need to define another set of pins.

I tend to think it'll work but not sure. Could someone assure me of that?:|

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Or is it more sensible to leave the schematic just as a typical SPI configuration. No extra pins defined or connected.

After FPGA configuration, use primitive STARTUPE2 to utilize CCLK, the other MOSI MISO CE pins could be reused directly by user logic.

Re: how to update flash with user logic?

Hi,

If you want someone to help you should at least say what IC´s are you talking about.
Otherwise statements like "CCLK is a dedicated pin" makes no sense.

A schematic is helpful, too. Post it.

How is it related to the FPGA? Do you want to store the FPGA config in the Flash, or do you want to program the FLASH via the FPGA, or both?

Did you do a search at the IC manufacutrers internet site?

Klaus

Re: how to update flash with user logic?

KlausST said:

Hi,

If you want someone to help you should at least say what IC´s are you talking about.
Otherwise statements like "CCLK is a dedicated pin" makes no sense.

A schematic is helpful, too. Post it.

How is it related to the FPGA? Do you want to store the FPGA config in the Flash, or do you want to program the FLASH via the FPGA, or both?

Did you do a search at the IC manufacutrers internet site?

Klaus

Click to expand...

Their question is about a Xilinx part, CCLK is the configuration clock, in SPI master mode the FPGA configures itself from a SPI flash device.

I don't really understand their question as it is documented, by Xilinx, on how to access the SPI flash device after configuration so you can upgrade the images or data in the SPI flash. They have app notes on this. This is also how the Xilinx tools can update a SPI flash attached to the device, it programs the FPGA with an images that supports SPI flash write via the Platform cable.

Re: how to update flash with user logic?

it's xilinx 7 serise, and CCLK is a dedicated pin. So I assume it could only be used via primitive, but not directly.

I'm having trouble uploading picture..the schematic is exactly the same as ug470, p51, figure2-12, the Master SPI mode.
https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

I intend to program FLASH through FPGA logic, that is, 1. generating .bin file; 2. trasmit it to FPGA; 3. user logic writes it to FLASH.
I had some questions that whether CCLK could be used by user logic? Later I found that by using primitive CCLK can be used after all.

Re: how to update flash with user logic?

Hi,

I'm having trouble uploading picture..

Click to expand...

Prepare the picture on your computer in PNG, JPG or BMP format.
In the EDIT or QUICK REPLY box just press the INSERT IMAGE button and follow the guide.

Klaus