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Never seen Deep Nwell process option mentioned for latchup prevention. It's good for isolation from substrate, by this achieves substrate noise reduction of -50dB .. -35dB for LF up to ≈ 100MHz, lower flicker noise for BJTs, and better RF transistors (lower parasitic substrate capacitances). Moreover, additional useful - otherwise called "parasitic" - devices are possible in deep n-wells: lateral npn BJTs with livable beta, and p-channel JFETs. The device layouts do not differ from orthodox layout designs - apart from spacing rules to the n-well borders, like for any well devices.
Can we safely draw the conclusion that deep nwell can prevent the SCR latchup between the nmos and its nearby pmos? Since the nmos transistor is embeded in the deep nwell, which isolate nmos and pmos, so the parasitic npn and pnp due to the SCR achitecture disappear.
However, as you mentioned, other parasitc devices are still there, which can form a pn junction, when they are forward bias, then latch-up occurs. Thanks.
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