LatticeSemiconductor
Member level 2
hello,
I just noticed this port map in the project I am working on:
I have never seen such a thing. What's its purpose, how does it work, how is this called? If this was to convert from one signal type to another I'd rather do it this way:
Is it perhaps equivalent?
I just noticed this port map in the project I am working on:
Code VHDL - [expand] 1 2 3 4 5 6 custom_fifo PORT map( clk => clk, . . . std_logic_vector(q) => q );
I have never seen such a thing. What's its purpose, how does it work, how is this called? If this was to convert from one signal type to another I'd rather do it this way:
Code VHDL - [expand] 1 2 3 4 5 6 custom_fifo PORT map( clk => clk, . . . q => std_logic_vector(q) );
Is it perhaps equivalent?