msdarvishi
Full Member level 4
Dear all,
I am using Vivad0 2017.1 on a Window 7-64bit laptop targeting a Zynq-7000 (xc7z020clg484-3) FPGA
I have a design that includes a 16-bits counter implemented successfully in the PL part of the FPGA. Based on the description in page 13 of zedboard user guide here, we know that UART 1 is already connected to the PS part of device which means there will be no connection from PL part to this UART. Please correct me if I am wrong !
Now, I want to send the output of my counter that are 16 bits to the UART port and read the counted values with a terminal (PuTTY, Tera term, Hyperterminal, etc). I searchd a lot about this issue even the Hell world project that was written in C language and is run in SDK !!! I am pretty confused !!
Something that I have done untill now, is shown in the attached snapshot. I have generated the IP core AXI UART16550 as an Out-of-context module along with mu top file (top file includes my counter). But after synthesis and implementation, I do not see the UART module and I do not know how should I define the outputs of counter to be sent to the UART and what constraints are required to make the UART run and send the counted values to the PC to be seen in terminal???
I am wondering if someone can guide me step by step to solve this issue. I am new to Zedboard. I also have read some post regarding enabling UART 0 in zedboard like here, but it's again written in C language while I have VHDL files for my counter !!!
Kind replies and helps are in advance appreciated.
Regards,
I am using Vivad0 2017.1 on a Window 7-64bit laptop targeting a Zynq-7000 (xc7z020clg484-3) FPGA
I have a design that includes a 16-bits counter implemented successfully in the PL part of the FPGA. Based on the description in page 13 of zedboard user guide here, we know that UART 1 is already connected to the PS part of device which means there will be no connection from PL part to this UART. Please correct me if I am wrong !
Now, I want to send the output of my counter that are 16 bits to the UART port and read the counted values with a terminal (PuTTY, Tera term, Hyperterminal, etc). I searchd a lot about this issue even the Hell world project that was written in C language and is run in SDK !!! I am pretty confused !!
Something that I have done untill now, is shown in the attached snapshot. I have generated the IP core AXI UART16550 as an Out-of-context module along with mu top file (top file includes my counter). But after synthesis and implementation, I do not see the UART module and I do not know how should I define the outputs of counter to be sent to the UART and what constraints are required to make the UART run and send the counted values to the PC to be seen in terminal???
I am wondering if someone can guide me step by step to solve this issue. I am new to Zedboard. I also have read some post regarding enabling UART 0 in zedboard like here, but it's again written in C language while I have VHDL files for my counter !!!
Kind replies and helps are in advance appreciated.
Regards,