tanish
Junior Member level 2
Hello
I'm trying to simulate a simple D Flip Flop in xilinx 14.7.I've wrote the testbench and I set the modelsim as simulator an I did the behavioral simulation without any problem but when I try to simulate the place & route simulation I can't see the result.
This is my code :
this is behavioral result:
this is timing result:
- - - Updated - - -
actually I should say ISE 14.7
I'm trying to simulate a simple D Flip Flop in xilinx 14.7.I've wrote the testbench and I set the modelsim as simulator an I did the behavioral simulation without any problem but when I try to simulate the place & route simulation I can't see the result.
This is my code :
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 module dff(in, clk, reset, q); input in; input clk; input reset; output reg q; always @ (posedge clk or posedge reset) begin if(reset) begin q = 1'b0; end else begin q = in; end end and this is the testbench : module dff_test; localparam T=10; // Inputs reg in; reg clk; reg reset; // Outputs wire q; // Instantiate the Unit Under Test (UUT) dff uut ( .in(in), .clk(clk), .reset(reset), .q(q) ); //defining clock always begin clk = 1'b0; #(T/2); clk = 1'b1; #(T/2); end //defining reset initial begin reset = 1'b1; #(T/2); reset = 1'b0; #(T/2); end //input vectors initial begin in = 1'b0; #(T); #(T/10); in = 1'b1; #(T); in = 1'b0; #(T); end endmodule
this is behavioral result:
this is timing result:
- - - Updated - - -
actually I should say ISE 14.7