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Verilog Assignment code

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hareeshP

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Hi All,
Please anyone tell me how the below code works?

Code Verilog - [expand]
1

assign  Reset = (a & cnt[19])? (ok_cnt[19]? b: 1'b1) : b;
 

Reset is assigned based on the conditions on the RHS.

? is the conditional operator in verilog:
(condition) ? (value when condition_is_true) : (value when condition_is_false);

Remember in verilog, like C, any non-zero value counts as true.

- - - Updated - - -

Btw - google will get you many Verilog tutorials - here is the first hit for me:
https://www.asic-world.com/verilog/veritut.html
 

can you please convert the above code into vhdl?
 

actually i am following the vhdl tutorial and i wants convert a verilog source code into vhdl one. So i need to understand the logic used in verilog.
 

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