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FPGA interfacing ADC with sampling rate >150 Msps

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sherif123

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I am about to select an FPGA for a system in which there are two ADCs with sampling rate more than 150MHz.
There are many choices for the FPGA model. I can use Altera or Xilinx.
I want to select the best FPGA model for this purpose. I can select from (Altera) Cyclone 5, Arria 5 or (Xilinx) Artix or Kintex.
I know that any of those can easily interface to that ADC, but I don't want just interfacing, but some data processing (Communication systems, correlation, some image processing, .....).
The main system block is not yet done so I cannot just synthesize and check the timing. So my question is what do you recommend for such application?
 

Hi

What interface, what ADC, how many ARC, are all the channels synchronized?
Data processing is a wide range from simple offset or gain correction up to real time 3D processing. Only you know the specifications.How much RAM, how many and what operations....

Klaus
 

I have an experience with the evaluation boards from Terasic: 'Cyclone V GX Starter Kit' and 'DCC AD/DA Data Conversion Card', although I haven't tried to run ADC at higher frequency that 150 MHz. Terasic/Altera provide some simple VHDL code to start with ADC/DAC. The ADC/DAC board is rather expensive, but you can download schematic and do your own daughter board (this one from Terasic is AC-coupled, so you may want to change this part of the design).
 

Thank you filip.amator

I did not select the ADC chip yet. The expected interface is LVDS. All the channels are synchronized.
For the RAM, I may need to add DDR3.
I already made boards with ADC/DAC with FPGAs, but my question is about your recommendation if the sampling rate is more than 150 MHz. Which FPGA is a practical choice?
 

Any recent Altera, Xilinx, Lattice etc. FPGA can acquire serialized LVDS data. Performance differences probably matter beyond 600 Mbps LVDS data rate.

DDR3 interface can be more challenging if you rely on write leveling support (required at least for DDR3 modules). It's only provided by some FPGA families.
 

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