mahmood.n
Member level 5
There is an up/down counter entity where the direction is first set to '1' to count up. Another entity can change the direction if a condition is met. So the test bench looks like
signal c: std_logic := '0'; -- clock
signal r: std_logic := '0'; -- reset
signal d: std_logic := '1'; -- direction
signal cou: integer range 0 to 7; -- count value
...
u0: counter port map( c, r, d, cou ); -- in, in, in, out
u1: reader port map( a, cou, c, d, z ); -- in, in, in, out, out
As you can see the 'd' is initialized to '1'. So, I expect that the counter counts up. However, in the simulation the value of 'd' is U. Well it is correct that assignment is not good because the input 'd' port of the counter receives two wire (one from the initialization and the other from reader).
The architecture of counter is
Any idea?
signal c: std_logic := '0'; -- clock
signal r: std_logic := '0'; -- reset
signal d: std_logic := '1'; -- direction
signal cou: integer range 0 to 7; -- count value
...
u0: counter port map( c, r, d, cou ); -- in, in, in, out
u1: reader port map( a, cou, c, d, z ); -- in, in, in, out, out
As you can see the 'd' is initialized to '1'. So, I expect that the counter counts up. However, in the simulation the value of 'd' is U. Well it is correct that assignment is not good because the input 'd' port of the counter receives two wire (one from the initialization and the other from reader).
The architecture of counter is
Code:
architecture behav of counter is
signal cnt: integer range 0 to 7:= 0;
begin
process( rst, clk )
begin
if (rst = '1') then
cnt <= 0;
elsif (clk'event and clk = '1') then
if dir = '1' then
cnt <= cnt + 1;
else
cnt <= cnt - 1;
end if;
end if;
end process;
z <= cnt;
end;