beginner_EDA
Full Member level 4
Hi,
I am trying to understand I2C using Picoblaze processor
https://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf
used in one reference design
https://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf
for
https://www.silabs.com/documents/public/data-sheets/Si5324.pdf
with address : 1101 000 R/W
Now I also need to control another components (in parallel with above one) with I2C with address : 1001 000 R/W.
Trying to find where is the address used in the program but unable to find.
As per picoblaze documenation(timing diagram page 47 and 50), address is in PORT_ID[7:0] which is coming 8 LSB bits from INSTRUCTION[17:0].
As per page 55 this INSTRUCTION[17:0] is coming from Block RAM. In block RAM of size 4096 with 9 bits width has initial value of 4096 written in one .coe file.
I didn't find where is the address 1101 000 R/W for Si5324. AS I mentioned my aim is to use 1001 000 R/W address to control another component in parallel.
Verilog/VHDL file is in attachments.
Any hints?
I am trying to understand I2C using Picoblaze processor
https://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf
used in one reference design
https://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf
for
https://www.silabs.com/documents/public/data-sheets/Si5324.pdf
with address : 1101 000 R/W
Now I also need to control another components (in parallel with above one) with I2C with address : 1001 000 R/W.
Trying to find where is the address used in the program but unable to find.
As per picoblaze documenation(timing diagram page 47 and 50), address is in PORT_ID[7:0] which is coming 8 LSB bits from INSTRUCTION[17:0].
As per page 55 this INSTRUCTION[17:0] is coming from Block RAM. In block RAM of size 4096 with 9 bits width has initial value of 4096 written in one .coe file.
I didn't find where is the address 1101 000 R/W for Si5324. AS I mentioned my aim is to use 1001 000 R/W address to control another component in parallel.
Verilog/VHDL file is in attachments.
Any hints?