hcu
Advanced Member level 4
Combinatorial loop and its effects ? how to avoid this ?
Hi,
my verilog code line at the end looks like this ,
assign Total_result = x ? result1 : y ? result2 : Total_result ;
This forms a combinatorial loop and linting tool shows error here and while vivado tool shows warning and tells timing may fail later.
how can i rewrite this,
if i use procedural assignment block like
always@(posedge clk)
Total_result = x ? result1 : y ? result2 : Total_result ;
This may remove error, but the result will consume 1 clock cycle more which i dont want.
some help is really appreciated.
Hi,
my verilog code line at the end looks like this ,
assign Total_result = x ? result1 : y ? result2 : Total_result ;
This forms a combinatorial loop and linting tool shows error here and while vivado tool shows warning and tells timing may fail later.
how can i rewrite this,
if i use procedural assignment block like
always@(posedge clk)
Total_result = x ? result1 : y ? result2 : Total_result ;
This may remove error, but the result will consume 1 clock cycle more which i dont want.
some help is really appreciated.
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