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help needed regarding thermal issues in layout design

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hi
i need some help on thermal effects/ issues in cmos circuit design and how they can be analysed. how to take care of it to reduces its effects while designing the layout.
If you have any material or links kindly let me know.
Thanks in advance
 

try this site https://www.cs.virginia.edu/~skadron/, it is the home page of Kevin Skadron, a prof in virginia who does a lot of work in fields you mentioned. tell me if this is what you had in mind and if yes i will try posting a few papers as well..
 

hi rkartik1
Thanks a lot for ur reply. I am looking for material related to thermal effects which come up while designing layout for a cmos intergrated circuit, and the ways how we can avoid them or reduce them.
If you have any material on this kindly let me know...

you can mail me on pkm_munot1@hotmail.com as i dont have enought points to download here..

Thanks in advance.
 

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