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Oversampling clock and data recovery for SerDes communication

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bit_an

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Dear Friends, I am newbie to hardware design. I have a task to design a burst mode CDR. Typically it should have very fast frequency acquisition time.
In my system, I have a 8 phase clock input. I am sampling my data with this clock. Now I am searching for an algorithm to detect the phase at the mid point of the data (thereby locks in no time). I think I should need a phase selector which is driven by this algorithm.
There are papers in the web related to the topic. But being new to this field some tips and examples would be very helpful.
 

Here are some updates.. Typically one needs an odd phase clock for this task if you aim for all digital design. An oversampling CDR would be a good option. Among the oversampling algorithms available, the one which has no FIFO is more hardware efficient and fast. However the design is bit more challenging. Still I could not ***** the algo. Especially how to realize it in hardware. In case you have some input, you are most welcome.
 

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