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[SOLVED] Techniques for system modeling in FPGAs

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hobbyiclearner

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Hi,

I wanted to know the available techniques for system modeling in FPGAs (using VHDL). One technique is FSM. Are there any other ways.

Thanks,
Hobbyiclearner.
 

This is a rather vague question. VHDL has a lot of language features for building behavioural models. What are you actually trying to do?
A FSM is just a way of building a circuit - or it could be used as part of a large design - it is not confined just to system modelling.
 

Its a general query. I wanted to know the possible ways of system designing. One technique is its implementation through FSM. What could be the other way(s).
Thanks,
Hobbyiclearner.
 

again, its not really a valid question. Every single design is really a FSM - it transitions through state A to get to state B. This may be a design with 1 flip flop or 100000 flops.
Using a FSM written in VHDL may be one way of doing it, or using a counter, or some other behavioural style.

System design is about getting data or control information from point A to point B. How you write the code is pretty unimportant.
 
Great. That helped. How to use counters to realise a system pls :grin:

Hobbyiclearner.
 

Again, a pretty useless question, as all the answers depend on the system.
Please ask a better question.
 

hobbyiclearner said:
Great. That helped. How to use counters to realise a system pls :grin:

Hobbyiclearner.
Click to expand...

I get the impression you think there are a bunch of electronics educators on this forum. Well from what I've seen it's more of a bunch of very experienced working/retired engineers that like to help out the next generation of engineers become better engineers. I think asking forum members to teach you design techniques is pushing the limits of the effort members are likely willing to devote to you. This is something that should be learned in school or if a hobbyist on your own by reading lots of books/papers/websites on the subject.
 

hobbyiclearner said:
Great. That helped. How to use counters to realise a system pls :grin:

Hobbyiclearner.
Click to expand...

Your reply reminds me of the undergrad course book - An Engineering Approach to Digital Design by William I. Fletcher
You'll find all what you need there.
 

dpaul said:
Your reply reminds me of the undergrad course book - An Engineering Approach to Digital Design by William I. Fletcher
You'll find all what you need there.
Click to expand...

I find the reviews on the book on Amazon rather interesting...seems either you see how to apply the concepts presented in the book, or you're basically unable to follow them (which is probably those that aren't really going to make it as engineers). Though admittedly the sample size of reviews is ridiculously small.
 

I am not asking to tell me about the entire theory / practical of the topic. Instead, just point me to some starting material like an article/ book etc.

It is the first time I have heard about this design technique and have no clue about it. Hence asking.

Thanks,
Hobbyiclearner
 

hobbyiclearner said:
I am not asking to tell me about the entire theory / practical of the topic. Instead, just point me to some starting material like an article/ book etc.

It is the first time I have heard about this design technique and have no clue about it. Hence asking.

Thanks,
Hobbyiclearner
Click to expand...

Well a counter is a state machine, so there really isn't much to tell. Just decode the count values like you would decode the states in a textbook FSM.
 

Perhaps another kind of ‘technique’ ( better saying, an improvement on the complexity of the FSM ), is the microcode fetch/decoder that runs inside microcontrollers, on which states not pre-defined run in a top layer, being what we call by firmware, changing dynamically its flow path. Anyway, as said above, there is no other way in the hardware leve to do the same feature as a FSM does.
 

OK... So I can infer that apart from designing using discrete gates and flip-flops directly, one can design systems using FSMs. There seems to be no other way. Hope I am right. Will wait fro few days before marking the post as 'solved'.

Thanks,
Hobbyiclearner.
 

Dataflow designs are also popular in FPGA design. In this style, multiple functional units are created and interact by computing outputs when the inputs are valid. A network of units is then constructed.

In this style, overall system control is distributed across all of the units -- there is no central controller.
 

vGoodtimes said:
Dataflow designs are also popular in FPGA design. In this style, multiple functional units are created and interact by computing outputs when the inputs are valid. A network of units is then constructed.

In this style, overall system control is distributed across all of the units -- there is no central controller.
Click to expand...

But each unit is still likely to use it's own FSM.
All logic is really just one big FSM.
 

TrickyDicky said:
But each unit is still likely to use it's own FSM.
All logic is really just one big FSM.
Click to expand...

I can't argue against this. "FSM" is a very generic term and I also often think of a design as either one big FSM or a big FSM with some jigglies due to async fifos/signals. The OP might be taking this to literally though, as the OP mentions the logical concept of a FSM as potentially different than an implementation method that can implement at least some/all FSMs.
 

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