Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Fixing congestion after post route stage

Status
Not open for further replies.

biju4u90

Full Member level 3
Joined
Dec 10, 2014
Messages
172
Helped
3
Reputation
6
Reaction score
3
Trophy points
18
Activity points
1,437
In my design, I am having some congestion after post route stage. What are the different methods I can use to reduce the congestion without going back to the previous stages?
 

if you are using special routing rules or constraints, you can make them softer. for instance, if clock is always 2W2S, you can make it 1W2S or something.

if the problem is related to a specific cell (think something like AOI22, lots of pins), you can replace it for simpler cells and run OPT followed by route again.

if you have max tran, max load, max fanout rules that are too strict, you can make them less strict but still within allowed values. OPT+route should take care of it for you.

if the problem is related to floorplanning that was too tight to begin with, then you likely need to rethink the design.
 
That was a wonderful explanation!! Thank you!! :)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top