timing constraints in Vivado

Hello All,

I want to write the timing constraints file in Vivado and I know that vivado constraints wizard will help me to do it. However I want to know if timing constraints have to be written for each and every logic design which we do in HDL. If yes then how do I calculate set up and hold time and period for my design? Another question is that how will I calculate critical path, multicycle path etc

If you are using an IP (Xilinx or other), in most cases a constraints file is provided. You just have to make sure that it is analyzed by Vivado. For a Xilinx IP constraint file it will be taken care by Vivado.
You need to write the constraints only for the ports in the top-level design, i.e. the ports for which pin placement has been done.

Also read this for in-depth analysis: Design Analysis and Closure Techniques

https://www.xilinx.com/support/docu...xilinx2014_1/ug906-vivado-design-analysis.pdf

Thanks for the reply. I shall go through the document.. Is it like for Vivado IPs, I don't need to bother about the timing constraints at all. If I write HDL code of my own, then how am i suppose to calculate the set up and hold times? Is set up and hold time applicable only for the design which is connected to the pins of the FPGA. What about the internal logic, will they also have set up and hold times? Where will find the values of set up and hold times for them?

Sunayana Chakradhar said:

Thanks for the reply. I shall go through the document.. Is it like for Vivado IPs, I don't need to bother about the timing constraints at all. If I write HDL code of my own, then how am i suppose to calculate the set up and hold times? Is set up and hold time applicable only for the design which is connected to the pins of the FPGA. What about the internal logic, will they also have set up and hold times? Where will find the values of set up and hold times for them?

Click to expand...

Once you understand STA you will realize this question is just well, the wrong question.

Timing constraints are to tell the tools such things as:

• I want to run my design at such_n_such MHz.
• I want my inputs to meet timing with an external part that has a X ns Tco.
• I want my outputs to meet timing with my DAC that has a Xns Tsu and Yns Th.
• I have W, X, Y, and Z clock domains where W and Z are synchronous and X and Y are asynchronous to every other clock.
• I have multicycle paths.
• I have a maximum delay between this and that.

You produce those timing constraints, the place and route attempts to meet those constraints, the STA tool checks the placed and routed design against those constraints to determine if the entire path from FF to FF, input to FF, FF to output, etc meet the constraints. The STA tool therefore calculates if the setup and hold time are met, not you. You don't look up setup and hold times and try to calculate the path, this isn't like doing design with SSI or MSI ICs and having to do the entire thing by hand.

That was a nice summarized reply ads-ee.
I was wondering how to pen down the answers to those bunch of Qs in the shortest way possible. That was why in #3 I added the pdf link, hoping that the OP would read it and understand it herself. :idea: