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Cadence Encounter CTS

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preethi19

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Hi i am beginner level in cadence Encounter and i am trying to do the PRE-CTS. Wat i did was i synthesized my design in synopsys added some delay and got the contraint file .sdc. In encounter i uploaded this file, i also loaded the timing library worst case file too. But whn i run PRE-CTS or POST-CTS i am getting WNS everything to be 0 and not with any value. Could anyone pls tell me why is this happening. Maybe i missed on a step or is der a way to include delay in Encounter itself. Can anyone pls help!!!
 

your post is so hard to follow. let's start by the very basics. have you done placement? if so, with which tool?
what is the meaning of "added some delay"? how did you add delay, and to what?
WNS zero means timing is passing. do a report timing, see if the critical path is non-zero.

so many things could be wrong. your netlist might be behavioral, your sdc might me poorly written, your setup might be wrong, etc.
 

Thank you for the reply!!! I appologize for the unclear description. I simulated my d flip flop in modelsim, verfied the functionality. Then loaded the d flip flop verilog code to synopsys design vision. I loaded link and target libraries and synthesized the design. Next i added delays to the input and output of the flip flop, gave clock latency, clk uncertainity and i was able to view the contraint file in synopsys wer i could notice the WNS. (it had a value, was not zero). Saved this file as .sdc

Next went to cadence encounter. Loaded the synthesized verilog file and the .sdc file too and then added power rings, and placed the design and checked placement and der was no violations. When i do PRE-CTS i am getting WNS value to be zero. This is the problem i am getting.

The synthesized file i did post synthesis simulation and i could observe the input delay and the logic. It was correct but in encounter i am facing the CTS problem. In Post-CTS the WNS is also zero.
 

preethi19 said:
Thank you for the reply!!! I appologize for the unclear description. I simulated my d flip flop in modelsim, verfied the functionality. Then loaded the d flip flop verilog code to synopsys design vision. I loaded link and target libraries and synthesized the design. Next i added delays to the input and output of the flip flop, gave clock latency, clk uncertainity and i was able to view the contraint file in synopsys wer i could notice the WNS. (it had a value, was not zero). Saved this file as .sdc

Next went to cadence encounter. Loaded the synthesized verilog file and the .sdc file too and then added power rings, and placed the design and checked placement and der was no violations. When i do PRE-CTS i am getting WNS value to be zero. This is the problem i am getting.

The synthesized file i did post synthesis simulation and i could observe the input delay and the logic. It was correct but in encounter i am facing the CTS problem. In Post-CTS the WNS is also zero.
Click to expand...

As ThisIsNotSam pointed out WNS (Worst Negative Slack) being 0 (zero) is a good thing, it means timing is passing. If this value is NON-ZERO then you've missed timing by that much.

The non-zero value before placement and CTS was because the clock is considered to be ideal (i.e. perfect with 0 skew), once the CTS was performed the added clock skew fixed the timing violations you previously had.
 
Oh thank you for the reply!!! I understand that performing CTS would add clock slew and hence it would correct the timing violations (meaning correcting the input delay) and it would make the WNS zero. But then in that case shouldn't i get the WNS to be 0 after performing CTS which is POST-CTS. But i am getting WNS 0 for PRE-CTS too ie before the clock tree synthesis is performed. Can anyone pls tell why this is. Also i don't understand how clock is ideal before CTS becoz i added clock latency and clk uncertainity too in synopsys and generated the .sdc file. So shouldn't i see atleast some WNS value in PRE-CTS. Plsss help!!!
 

hi

Because cts adds buffers and real skew an insertion delay (latency) info we get is correct as clock is synthesized.Till then it exists only in sdc and for computing values.
 

preethi19 said:
Oh thank you for the reply!!! I understand that performing CTS would add clock slew and hence it would correct the timing violations (meaning correcting the input delay) and it would make the WNS zero. But then in that case shouldn't i get the WNS to be 0 after performing CTS which is POST-CTS. But i am getting WNS 0 for PRE-CTS too ie before the clock tree synthesis is performed. Can anyone pls tell why this is. Also i don't understand how clock is ideal before CTS becoz i added clock latency and clk uncertainity too in synopsys and generated the .sdc file. So shouldn't i see atleast some WNS value in PRE-CTS. Plsss help!!!
Click to expand...

I think you are mixing up different concepts. Make sure you understand what WNS is, and how it relates to propagated clock versus ideal clock.
 

Hi

Since It is a simple Flip flop you are seeing no violation. For bigger designs it will become more complex. BTW, for a single flip flop design you can directly verify the timing by dynamic style, no need for static.

Thanks.
 

WNS = 0, I have a doubt on this. I guess you are in the uncertained case of "No path" or "No violation".
Are you sure you have any "constrained" timing path ?

Back to logic point of view, in your case, there is only 1 Flipflop in design, no other cells.
Do you have ports connected from top to input/output of the FFlop ?
 

this thread is from June. I doubt OP is still around.
 

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