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Vivado Memory Mapped to Stream Mapper vs AXI4 to Stream FIFO

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shaiko

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Hello,

I'm trying to understand the difference between the following Vivado cores:

https://www.xilinx.com/support/docu...on/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf
vs
https://www.xilinx.com/support/docu...xi_mm2s_mapper/v1_1/pg102-axi-mm2s-mapper.pdf

In the 6th page of the first document it's written:
The AXI4-Stream FIFO core converts AXI4/AXI4-Lite transactions to and from AXI4-Stream
transactions
Click to expand...
But isn't this the whole purpose of the mapper (2nd document)?
When should we use one and not the other?
 

The "AXI4-Stream FIFO" is used to communicate with some other block that has an AXI4 stream interface.

The "AXI Memory Mapped to Stream Mapper" must be used in pairs. They communicate between each other with an AXI4 stream interface but the interface to other blocks is memory mapped in both ends. It is only an "extension".
 
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The "AXI4-Stream FIFO" is used to communicate with some other block that has an AXI4 stream interface.
Click to expand...

I understand.
But the FIFO's datasheet explicitly notes that the very purpose of this IP is to convert from AXI MM to AXI Stream.
So why bother using the Mapper IP instead?
 

The difference is the AXI4-Stream FIFO is used to generate stream data packets on an AXI4-S link.
The AXI Memory Mapped to Stream Mapper is used to communicate with an AXI4 MM slave on the other side of an AXI4-S link.

Sure you can use the AXI4-S FIFO to do this but you would have to add a protocol layer for the transfer to allow it to be decode for an AXI4 MM slave, basically just reinventing what the AXI-MM to AXI4-S Mapper already does.
 
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So the AXI4-S FIFO only works one way, I.E - MM input, Stream output?
It can't be configured to do the opposite function (receive a stream and decode it to MM)?
 

You can connect two AXI4-S FIFO's but it will not be transparent since the MM interface will be a slave in both ends.

The AXI4 MM to stream mapper is intended for making a transparent "extension" of a memory mapped interface. It is an MM slave in one end and an MM master in the other end. The units that communicate will not know that there is a streaming interface involved.
 
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I'm pretty sure that is the case
Click to expand...
If the FIFO can only receive Memory Mapped and transmit Stream (while not vice versa)
What's the purpose of AXI_STR_RXD bus (page 9) ?
 

shaiko said:
If the FIFO can only receive Memory Mapped and transmit Stream (while not vice versa)
What's the purpose of AXI_STR_RXD bus (page 9) ?
Click to expand...

Okay it's bi-directional, but that still doesn't mean it's capable of memory mapped bridging, as both sides of the interface would have slave MM to master Stream. Unlike the M2S mapper which has a MM slave to Stream master <=> Stream slave to MM master, which makes it a MM to MM bridge.
 
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