Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

alwasy@(*) equivalent in VHDL

Status
Not open for further replies.

Shashidhara

Newbie level 1
Joined
May 19, 2016
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
9
Hi,

We have always@(*) flexibility to add all the signals in the sensitivity list.

do we have anything equivalent in VHDL something like process(*)

Thanks in advance
Shashidhara
 

Process(all)
 

process(all) is the answer with VHDL 2008
There is no equivalent in VHDL '93
 

also no equivalent in verilog in 1993, 23 years ago.

complain to tool vendors if you want vhdl-2008 support in 2016.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top