Shashidhara
Newbie level 1
Hi,
We have always@(*) flexibility to add all the signals in the sensitivity list.
do we have anything equivalent in VHDL something like process(*)
Thanks in advance
Shashidhara
We have always@(*) flexibility to add all the signals in the sensitivity list.
do we have anything equivalent in VHDL something like process(*)
Thanks in advance
Shashidhara