Vivado pin planning issues

Hello All,

I have received an excel sheet from my PCB designer for ZC7020 SoC. I need to do pre synthesis pin planning for the same and check the DRC. I need to create IO ports, set IO standards and direction of the ports. I want to know 2 things.

1. I am using almost all 400 pins on the SoC. Should I manually create the IO ports?
2. There is an option in the vivado pin planning tool where in i can import IO ports in the form of a .xdc or .csv file. When I tried doing this, it will import only the site names and the bank numbers. It doesn't automatically set the IO standards nor the directions.

3. Is DRC checked only for the non PS pins (Bank 13,33,34). Bank 500, 501, 502 are the PS MIO pins and there is no user accessibility on them. They cannot be made into ports at all.

I am a little confused as i have to create IO ports manually each time. Please clarify.

Sunayana Chakradhar said:

I have received an excel sheet from my PCB designer for ZC7020 SoC. I need to do pre synthesis pin planning for the same and check the DRC. I need to create IO ports, set IO standards and direction of the ports. I want to know 2 things.

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Good luck with that, I would never let the typical PCB designer pick the pinout of an FPGA, every design that I've seen that had that done was respun because of a major screw up in the pin assignments. Only someone experienced in FPGA design who just happens to be doing a board would I expect to get this right.

1. I am using almost all 400 pins on the SoC. Should I manually create the IO ports?

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see above answer...using nearly all the pins just makes the job harder and more likely to be wrong (when done by the typical PCB designer).

2. There is an option in the vivado pin planning tool where in i can import IO ports in the form of a .xdc or .csv file. When I tried doing this, it will import only the site names and the bank numbers. It doesn't automatically set the IO standards nor the directions.

Click to expand...

it should import anything that is in the xdc file for the port if it was defined in the first place. If I'm stuck importing from a .csv file I usually just write a script in Perl to read the .csv file and export a a xdc file with all the relevant information per pin.

3. Is DRC checked only for the non PS pins (Bank 13,33,34). Bank 500, 501, 502 are the PS MIO pins and there is no user accessibility on them. They cannot be made into ports at all.

Click to expand...

have no input on this as I've never worked with the SoC parts, though I'm interested in trying this out.

I am a little confused as i have to create IO ports manually each time. Please clarify.

Click to expand...

I usually do this manually as it's mostly a cut and paste operation with column numbering updates for buses.