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UART fifo full, it is possible to increase it?

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Ananhasaasneh77

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uart fifo full , it's is possible to increase it?

hello guys, sry for being annoying ..

from pang chu book

The full and empty status of the respective FIFO buffers can be
tested by consecutively receiving and transmitting more than four data words.
Click to expand...

my question is it possible to increase the number of data word that fifo can contain
in the uart code the fifo just 4 data words like when u send from hypertermianl word "" hello ""
the fpga board turn it back like this "hellh"

it is possible to increase it, to make the word " hello " when i send from hypertermianl to fpga .. the fpga turn it back to hyperwindow " hello" not hellh"?

if it possible how can i do it ? if it not, why??!

sryy .. thanks alot ..
 

Re: uart fifo full , it's is possible to increase it?

How do you know if it's the FIFO that is causing this issue? Have you run a simulation that proves this or have you chipscoped/signaltapped the design to prove it's happening in the hardware?

If you have access to unencrypted source code it's probably very easy to increase the FIFO size. Of course you once again have not supplied anything of use to determine if it's easy or not.

You are only being annoying by NOT giving anyone useful data to help you.

- - - Updated - - -

Edit...
Was wondering what book you were reading the authors name is Pong P. Chu and they seem to have a number of books that have pretty good reviews on Amazon. So I suppose at least you've made a decent book choice to learn HDL coding.
 

Re: uart fifo full , it's is possible to increase it?

How do you know if it's the FIFO that is causing this issue? Have you run a simulation that proves this or have you chipscoped/signaltapped the design to prove it's happening in the hardware?
Click to expand...
no i didnt becuz i dont knw how to do that.

If you have access to unencrypted source code it's probably very easy to increase the FIFO size. Of course you once again have not supplied anything of use to determine if it's easy or not.
Click to expand...

what u want me to supply ?
 

Re: uart fifo full , it's is possible to increase it?

Ananhasaasneh77 said:
no i didnt becuz i dont knw how to do that.
Click to expand...
then learn how to run simulations if you want to keep trying to do design work. Also if you have the license learn to use chipscope/signaltap as it's like having a logic analyzer in the FPGA instead of having to route all the signals to pins to hook up an external one.

what u want me to supply ?
Click to expand...
for starters you could have just supplied the code which controls the FIFO and the FIFO code itself and make sure it's not just some top level with instances of other modules which you don't supply (something you've done previously). Having a top-level file is like having the chapter names of a book without the chapter text.
 

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