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[SOLVED] Help with synthesis signals and sensitivity list

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Tychus

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Hi,

I'm a newbie when it comes to VHDL, synthesis and all what goes with. I'm having hard time with an assignment where i have to design a Fibonacci generator. i wrote a code with a test bench everything working fine until i tried to synthesize it using cadence; i got two warning messages that says :

" Referenced signal not in sensitivity list. This may cause simulation mismatches between the original and synthesized designs. "

it warned me about signals b and c. after the synthesis the netlist generated did not produce the correct output.

VHDL code :

Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity fibonacci is
 port(
      clk, rst : in std_logic;
      limit : in std_logic_vector(9 downto 0);
      fibo_series: out std_logic_vector(9 downto 0)
      );
end fibonacci;

architecture fibonacci of fibonacci is
 signal a,b,c : std_logic_vector(9 downto 0);
begin
 process(clk,rst)
 begin
  if(rst = '1') then
   b <= std_logic_vector(to_unsigned(1, limit'length));
   c <= std_logic_vector(to_unsigned(0, limit'length));
  elsif(clk'event and clk='1') then
   if(c = limit) then
	   b <= std_logic_vector(to_unsigned(1, limit'length));
 	   c <= std_logic_vector(to_unsigned(0, limit'length));
   else	
	   c<=b;
 	   b<=a;
   end if;
  end if;
  a <= std_logic_vector(unsigned(b) + unsigned(c));
 end process;
 fibo_series <= c;
end fibonacci;

can anyone help with this issue ? do i have to add those signals to the sensitivity list ? i did not do it because it did not make sense to me.

Thank you
 

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Because you have the following problem in your code:


Code VHDL - [expand]
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process(clk,rst)
 begin
  if(rst = '1') then
    -- reset code
  elsif(clk'event and clk='1') then
    -- clock code
  end if;
 
  -- more code that is now combinational
  a <= std_logic_vector(unsigned(b) + unsigned(c));
 
 end process;
 fibo_series <= c;


move the a assignment to outside the process, or inside the end if, if that is the intent.

This is why good formatting and judicious use of whitespace (blank lines) helps in seeing mistakes like this.
 
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    Tychus

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