uart with sd controller

Ananhasaasneh77 · May 13, 2016

hello..

im trying to use uart with sd controller ..

sd controller will act like master to make connect with spi slave..

i checked the connection between sd controller and spi slave between 2boards and everything is okay..
but i want to use hyperterminal to send data through uart cable . i assigned rx tx on ucf also the leds ..
but i didnt got any led lights on when i write sth on hyperterminal ..
any idea on my problem?

there is the top code.. sd controller :

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sd_controller is

Generic 
		( 	
			Div : natural := 62;							-- dzielnik zegara 50 MHz / 250 -> 400 kHz
			Div2 : natural := 1							-- dzielnik zegara 50 MHz / 250 -> 400 kHz
			
		 );

port (
	cs : out std_logic;
	mosi : out std_logic;
	miso : in std_logic;
	sclk : out std_logic;
	
	--seg : out std_logic;
	--an : out std_logic;
	test_tick_button : out std_logic;
	--level_button : out std_logic;
	--level_button : out std_logic;

	rd : in std_logic;
	wr : in std_logic;
	dm_in : in std_logic;	-- data mode, 0 = write continuously, 1 = write single block
	reset : in std_logic;
	din : in std_logic_vector(7 downto 0);
	dout : out std_logic_vector(7 downto 0);
	clk : in std_logic;	-- twice the SPI clk
	
	
	  zapis_fifo: out std_logic;
	  
	  clk1600: out std_logic;
	  clk400: out std_logic;
	  

	
		btn: in std_logic_vector(2 downto 0);
		wysw2_btn: in std_logic;
      rx: in std_logic;
      tx: out std_logic;
      led: out std_logic_vector(7 downto 0);
		
		an: out std_logic_vector(5 downto 0);  -- cyfra wyœwietlacza
      sseg: out std_logic_vector(7 downto 0) -- 
	
);

end sd_controller;

architecture rtl of sd_controller is
type states is (
	RST,
	INIT,
	CMD0,
	CMD58,
	CMD41,
	POLL_CMD,
	
	WAIT_BUTTON,
	WAIT_SEND,
	R3_0,
	R3_1,
	R3_2,
	R3_3,
	R3_4,
	R3_11,
	R3_22,
	R3_33,
	R3_44,
  
	IDLE,	-- wait for read or write pulse
	READ_BLOCK,
	READ_BLOCK_WAIT,
	READ_BLOCK_DATA,
	READ_BLOCK_CRC,
	SEND_CMD,
	RECEIVE_BYTE_WAIT,
	RECEIVE_BYTE,
	WRITE_BLOCK_CMD,
	WRITE_BLOCK_INIT,		-- initialise write command
	WRITE_BLOCK_DATA,		-- loop through all data bytes
	WRITE_BLOCK_BYTE,		-- send one byte
	WRITE_BLOCK_WAIT		-- wait until not busy
);


-- one start byte, plus 512 bytes of data, plus two FF end bytes (CRC)
constant WRITE_DATA_SIZE : integer := 515;

signal led5, led4, led3, led2, led1, led0: std_logic_vector(7 downto 0);

signal state, return_state : states;
signal sclk_sig : std_logic := '0';
signal cmd_out : std_logic_vector(55 downto 0);
signal recv_data : std_logic_vector(39 downto 0);
signal address : std_logic_vector(31 downto 0);
signal cmd_mode : std_logic := '1';
signal data_mode : std_logic := '1';
signal response_mode : std_logic_vector (1 downto 0) := "01";
signal data_sig : std_logic_vector(7 downto 0) := x"00";


signal to_fifo : std_logic_vector(7 downto 0) := x"00";


signal cnt: std_logic_vector (29 downto 0) := (others=>'0');
signal cnt2: std_logic_vector (29 downto 0) := (others=>'0');
signal clk1600kHz: std_logic :='0';
signal clk400kHz: std_logic :='0';

signal count : unsigned(9 downto 0); --will count from 0 to 2^10-1


	signal tx_full, rx_empty: std_logic;
   signal rec_data,rec_data1: std_logic_vector(7 downto 0);
   signal odpowiedzR3: std_logic_vector(39 downto 0);
   signal odpowiedzR1: std_logic_vector(7 downto 0);
   signal btn_tick: std_logic;
   signal write_uart_fifo_tx: std_logic :='0';
   signal wrr: std_logic :='0';
   signal button: std_logic :='1';
   signal level_button: std_logic :='1';
	signal odpowiedz : std_logic_vector (39 downto 0);
	signal dp_v : std_logic_vector (5 downto 0);
	
begin
  
  button <=not btn(0);
  --an <= '1';
  --seg <= level_button;
  test_tick_button <= btn_tick;
	
	--odpowiedz<=x"000000abcd";
	
   sseg_unit_0: entity work.hex_to_sseg
      port map(hex=>odpowiedz(39 downto 36), dp =>dp_v(0), sseg=>led0);
   -- instance for 4 MSBs of input
   sseg_unit_1: entity work.hex_to_sseg
      port map(hex=>odpowiedz(35 downto 32), dp =>dp_v(1), sseg=>led1);
   -- instance for 4 LSBs of incremented value
   sseg_unit_2: entity work.hex_to_sseg
      port map(hex=>odpowiedz(31 downto 28), dp =>dp_v(2), sseg=>led2);
   -- instance for 4 MSBs of incremented value
   sseg_unit_3: entity work.hex_to_sseg
      port map(hex=>odpowiedz(15 downto 12), dp =>dp_v(3), sseg=>led3);
	-- instance for 4 MSBs of incremented x2 value
   sseg_unit_4: entity work.hex_to_sseg
      port map(hex=>odpowiedz(7 downto 4), dp =>dp_v(4), sseg=>led4);
	-- instance for 4 MSBs of incremented x2 value
   sseg_unit_5: entity work.hex_to_sseg
      port map(hex=>odpowiedz(3 downto 0), dp =>dp_v(5), sseg=>led5);

   -- instantiate 7-seg LED display time-multiplexing module
   disp_unit: entity work.disp_mux
      port map(
         clk=>clk, reset=>'0',
         in0=>led0, in1=>led1, in2=>led2, in3=>led3, in4=>led4, in5=>led5,
         an=>an, sseg=>sseg);
  
   uart_unit: entity work.uart(str_arch)
      port map(clk=>clk, reset=>not reset, rd_uart=>btn_tick,
               wr_uart=> write_uart_fifo_tx,  --  impuls do zapisania wartoœci do w_data z rec_data1
               --wr_uart=> wrr,  --  impuls do zapisania wartoœci do w_data z rec_data1
					rx=>rx, 
					--w_data=> odpowiedz(7 downto 0), -- w_data -> dane wpisywane do kolejki FIFO_tx
					w_data=> to_fifo, -- w_data -> dane wpisywane do kolejki FIFO_tx
               tx_full=>tx_full, rx_empty=>rx_empty,
               r_data=>rec_data, tx=>tx);
  
   btn_db_unit: entity work.debounce(fsmd_arch)
      port map(clk=>clk400kHz, reset=> (not reset), sw=> button,
               db_level=>level_button, db_tick=>btn_tick);
  
  
  clock_divider: process (clk)
	begin
		if (rising_edge(clk)) then
			if (cnt < Div) then 
				cnt <= cnt+1;
			else
				cnt <= (others=>'0');
				clk400kHz <= not clk400kHz;
			end if;
		end if;
	end process clock_divider;
	--clk1600<=clk1600kHz;
	
--	clock_divider2: process (clk1600kHz)
--	begin
--		if (rising_edge(clk1600kHz)) then
--			if (cnt2 < Div2) then 
--				cnt2 <= cnt2+1;
--			else
--				cnt2 <= (others=>'0');
--				clk400kHz <= not clk400kHz;
--			end if;
--		end if;
--	end process clock_divider2;
		clk400<=clk400kHz;


  
	process(clk400kHz ,reset)
		variable byte_counter : integer range 0 to WRITE_DATA_SIZE;
		variable bit_counter : integer range 0 to 160;
		
	begin
		data_mode <= dm_in;

		if rising_edge(clk400kHz) then
			
			 count <= count + 1;

			
			if (reset='0') then
				state <= RST;
				sclk_sig <= '0';
			else
				case state is
				
				when RST =>
					sclk_sig <= '0';
					cmd_out <= (others => '1');
					address <= x"00000000";
					byte_counter := 0;
					cmd_mode <= '1'; -- 0=data, 1=command
					response_mode <= "01";	-- 0=data, 1=command
					bit_counter := 160;
					cs <= '1';
					state <= INIT;
										write_uart_fifo_tx <='0';

				
				when INIT =>		-- CS=1, send 80 clocks, CS=0
					if (bit_counter = 0) then
						cs <= '0';
						state <= CMD0;
					else
						bit_counter := bit_counter - 1;
						sclk_sig <= not sclk_sig;
					end if;
					write_uart_fifo_tx <='0';
					
				
				when CMD0 =>
					write_uart_fifo_tx <='0';
					cmd_out <= x"FF400000000095";
					bit_counter := 55;
					return_state <= CMD58;
					response_mode<="01";
					state <= SEND_CMD;

				when CMD58 =>
					write_uart_fifo_tx <='0';
					cmd_out <= x"FF7A0000000001";	-- 58d OR 40h = 7Ah
					bit_counter := 55;
					return_state <= CMD41;
					response_mode<="10";
					state <= SEND_CMD;
				
				when CMD41 =>
					write_uart_fifo_tx <='0';
					cmd_out <= x"FF690000000001";	-- 41d OR 40h = 69h
					bit_counter := 55;
					return_state <= POLL_CMD;
					response_mode<="01";
					state <= SEND_CMD;
			
				when POLL_CMD =>
					write_uart_fifo_tx <='0';
					if (recv_data(0) = '0') then
						state <= IDLE;
					else
						state <= CMD58; --CMD55
					end if;
        	
				when IDLE => 
					if (rd = '1') then
						state <= READ_BLOCK;
					elsif (wr='1') then
						state <= WRITE_BLOCK_CMD;
					else
						state <= IDLE;
					end if;
				
				when READ_BLOCK =>
					cmd_out <= x"FF" & x"51" & address & x"FF";
					bit_counter := 55;
					return_state <= READ_BLOCK_WAIT;
					state <= SEND_CMD;
				
				when READ_BLOCK_WAIT =>
					if (sclk_sig='1' and miso='0') then
						state <= READ_BLOCK_DATA;
						byte_counter := 511;
						bit_counter := 7;
						return_state <= READ_BLOCK_DATA;
						state <= RECEIVE_BYTE;
					end if;
					sclk_sig <= not sclk_sig;

				when READ_BLOCK_DATA =>
					if (byte_counter = 0) then
						bit_counter := 7;
						return_state <= READ_BLOCK_CRC;
						state <= RECEIVE_BYTE;
					else
						byte_counter := byte_counter - 1;
						return_state <= READ_BLOCK_DATA;
						bit_counter := 7;
						state <= RECEIVE_BYTE;
					end if;
			
				when READ_BLOCK_CRC =>
					bit_counter := 7;
					return_state <= IDLE;
					address <= std_logic_vector(unsigned(address) + x"200");
					state <= RECEIVE_BYTE;
        	
				when SEND_CMD =>
					if (sclk_sig = '1') then
						if (bit_counter = 0) then
							state <= RECEIVE_BYTE_WAIT;
						else
							bit_counter := bit_counter - 1;
							cmd_out <= cmd_out(54 downto 0) & '1';
						end if;
					end if;
					sclk_sig <= not sclk_sig;
				
				when RECEIVE_BYTE_WAIT =>
					if (sclk_sig = '1') then
						if (miso = '0') then
							recv_data <= (others => '0');
							if (response_mode="00") then
								bit_counter := 3; -- already read bits 7..4
							elsif (response_mode="01") then
								bit_counter := 6; -- already read bit 7
							elsif (response_mode="10") then
								bit_counter := 38; -- already read bit 39
							end if;
							state <= RECEIVE_BYTE;
						end if;
					end if;
					sclk_sig <= not sclk_sig;

				when RECEIVE_BYTE =>
					if (sclk_sig = '1') then
					
						
						--recv_data <= recv_data(6 downto 0) & miso;
						recv_data <= recv_data(38 downto 0) & miso;
						if (bit_counter = 0) then
							
							if (response_mode="00") then							
							--dout <= recv_data(6 downto 0) & miso;
								odpowiedzR1 <= recv_data(6 downto 0) & miso;
							elsif (response_mode="01") then
								odpowiedzR1 <= recv_data(6 downto 0) & miso;
							elsif (response_mode="10") then
								odpowiedzR3 <= recv_data(38 downto 0) & miso; -------------------------------------------------------
							end if;
								
							if(tx_full = '0') then
								rec_data1 <= std_logic_vector(unsigned(recv_data(7 downto 0)));
								--write_uart_fifo_tx <='1';
							end if;
							
							--led <= recv_data (15 downto 8);
							state <= WAIT_SEND;
						else
							bit_counter := bit_counter - 1;
							write_uart_fifo_tx <='0';
						end if;
					end if;
					sclk_sig <= not sclk_sig;
					
				when WAIT_SEND =>
					
					
						if (response_mode="01") then
							odpowiedz (7 downto 0) <= odpowiedzR1;
							odpowiedz (39 downto 8) <= x"00000000";
							dp_v <= "001111";
							
							to_fifo<=odpowiedzR1;
							write_uart_fifo_tx <='1';
							
							state <= WAIT_BUTTON;
							
							led <= "00000001";
						elsif (response_mode="10") then
							odpowiedz <= odpowiedzR3;
							dp_v <= "000000";
							
							to_fifo<=odpowiedzR3(7 downto 0);
							write_uart_fifo_tx <='1';
							state <= R3_0;
							led <= "00000011";

						end if;
					

						
					--led <= odpowiedz (15 downto 8);
				when R3_0 =>
						write_uart_fifo_tx <='0';
						--state <= R3_1;
						led <= "00000111";
						
						if count = 0 then
							state <= R3_1;
						else 
							state <= R3_0;
						end if;

				when R3_1 =>
						to_fifo<=odpowiedzR3(15 downto 8);
						write_uart_fifo_tx <='1';
						--state <= R3_11;
													led <= "00001111";
						if count = 0 then
							state <= R3_11;
						else 
							state <= R3_1;
						end if;

				when R3_11 =>
						write_uart_fifo_tx <='0';
						state <= R3_2;
													led <= "00011111";
						if count = 0 then
							state <= R3_2;
						else 
							state <= R3_11;
						end if;

				when R3_2 =>
						to_fifo<=odpowiedzR3(23 downto 16);
						write_uart_fifo_tx <='1';
						state <= R3_22;
					led <= "00111111";
					if count = 0 then
							state <= R3_22;
						else 
							state <= R3_2;
						end if;
				when R3_22 =>
						write_uart_fifo_tx <='0';
						state <= R3_3;
						led <= "01111111";
						if count = 0 then
							state <= R3_3;
						else 
							state <= R3_22;
						end if;
				when R3_3 =>
						to_fifo<=odpowiedzR3(31 downto 24);
						write_uart_fifo_tx <='1';
						state <= R3_33;
						if count = 0 then
							state <= R3_33;
						else 
							state <= R3_3;
						end if;
				when R3_33 =>
						write_uart_fifo_tx <='0';
						state <= R3_4;
						if count = 0 then
							state <= R3_4;
						else 
							state <= R3_33;
						end if;
				when R3_4 =>
						to_fifo<=odpowiedzR3(39 downto 32);
						write_uart_fifo_tx <='1';
						state <= WAIT_BUTTON;
						
					
				
				when WAIT_BUTTON =>
					write_uart_fifo_tx <='0';

					if (btn_tick = '1') then
						state <= return_state;
					else
						state <= WAIT_BUTTON;
					end if;
				
				when WRITE_BLOCK_CMD =>
					cmd_mode <= '1';
					if (data_mode = '0') then
						cmd_out <= x"FF" & x"59" & address & x"FF";	-- continuous
					else
						cmd_out <= x"FF" & x"58" & address & x"FF";	-- single block
					end if;
					bit_counter := 55;
					return_state <= WRITE_BLOCK_INIT;
					state <= SEND_CMD;
					
				when WRITE_BLOCK_INIT => 
					cmd_mode <= '0';
					byte_counter := WRITE_DATA_SIZE; 
					state <= WRITE_BLOCK_DATA;
					
				when WRITE_BLOCK_DATA => 
					if byte_counter = 0 then
						state <= RECEIVE_BYTE_WAIT;
						return_state <= WRITE_BLOCK_WAIT;
						response_mode <= "00";
					else 	
						if ((byte_counter = 2) or (byte_counter = 1)) then
							data_sig <= x"FF"; -- two CRC bytes
						elsif byte_counter = WRITE_DATA_SIZE then
							if (data_mode='0') then
								data_sig <= x"FC"; -- start byte, multiple blocks
							else
								data_sig <= x"FE"; -- start byte, single block
							end if;
						else
							-- just a counter, get real data here
							data_sig <= std_logic_vector(to_unsigned(byte_counter,8));
						end if;
						bit_counter := 7;
						state <= WRITE_BLOCK_BYTE;
						byte_counter := byte_counter - 1;
					end if;
				
				when WRITE_BLOCK_BYTE => 
					if (sclk_sig = '1') then
						if bit_counter=0 then
							state <= WRITE_BLOCK_DATA;
						else
							data_sig <= data_sig(6 downto 0) & '1';
							bit_counter := bit_counter - 1;
						end if;
					end if;
					sclk_sig <= not sclk_sig;
					
				when WRITE_BLOCK_WAIT =>
					response_mode <= "01";
					if sclk_sig='1' then
						if MISO='1' then
							if (data_mode='0') then
								state <= WRITE_BLOCK_INIT;
							else
								address <= std_logic_vector(unsigned(address) + x"200");
								state <= IDLE;
							end if;
						end if;
					end if;
					sclk_sig <= not sclk_sig;

				when others => state <= IDLE;
        end case;
      end if;
    end if;
  end process; 
 
  sclk <= sclk_sig;
  mosi <= cmd_out(55) when cmd_mode='1' else data_sig(7);
  
  dout <= odpowiedz (7 downto 0);
  
  zapis_fifo<=write_uart_fifo_tx;
  
--  process (clk1600kHz,write_uart_fifo_tx)
--  
--  begin
--		if (rising_edge(clk1600kHz)) then
--			if(rising_edge(write_uart_fifo_tx)) then
--				wrr<='1';
--			else
--				wrr<='0';
--			end if;
--		end if;
--					
--	
--  end process;
  
  
--  zapis_do_fifo : process (clk, wyslij, response_mode, odpowiedzR1, odpowiedzR3)
--	variable poczekaj : integer range 0 to 160;
-- 
--  begin
--  
--		if (wyslij = '1') then
--			poczekaj := 160;
--			if (response_mode="01") then
--			
--					to_fifo<=odpowiedzR1;
--					write_uart_fifo_tx <='1';
--			
--			elsif (response_mode="10") then
--					
--					if (poczekaj = 150) then 
--						to_fifo<=odpowiedzR3(7 downto 0);
--						write_uart_fifo_tx <='1';
--					elsif (poczekaj = 120) then 
--						to_fifo<=odpowiedzR3(15 downto 8);
--						write_uart_fifo_tx <='1';
--					elsif (poczekaj = 90) then 
--						to_fifo<=odpowiedzR3(23 downto 16);
--						write_uart_fifo_tx <='1';
--					elsif (poczekaj = 60) then 
--						to_fifo<=odpowiedzR3(31 downto 24);
--						write_uart_fifo_tx <='1';
--					elsif (poczekaj = 30) then 
--						to_fifo<=odpowiedzR3(39 downto 32);
--						write_uart_fifo_tx <='1';
--					else
--						write_uart_fifo_tx <='0';
--					end if;
--				
--			end if;
--			
--			poczekaj:= poczekaj - 1;
--
--		end if;
--	
--  end process;
  
end rtl;

the ucf file

Code:

## This file is a general .ucf for Nexys3 rev B board
## To use it in a project:
## - remove or comment the lines corresponding to unused pins
## - rename the used signals according to the project

##Clock signal
Net "clk400" LOC=V10 | IOSTANDARD=LVCMOS33;
Net "clk400" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;

## onBoard USB controller
#Net "EppAstb" LOC = H1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41N_GCLK26_M3DQ5, Sch name = U-FLAGA
#Net "EppDstb" LOC = K4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = U-FLAGB
#Net "EppWait" LOC = C2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83P, Sch name = U-SLRD
#Net "EppDB<0>" LOC = E1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50N_M3BA2, Sch name = U-FD0
#Net "EppDB<1>" LOC = F4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P_M3A10, Sch name = U-FD1
#Net "EppDB<2>" LOC = F3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N_M3A4, Sch name = U-FD2
#Net "EppDB<3>" LOC = D2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52P_M3A8, Sch name = U-FD3
#Net "EppDB<4>" LOC = D1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L52N_M3A9, Sch name = U-FD4
#Net "EppDB<5>" LOC = H7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53P_M3CKE, Sch name = U-FD5
#Net "EppDB<6>" LOC = G6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L53N_M3A12, Sch name = U-FD6
#Net "EppDB<7>" LOC = E4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54P_M3RESET, Sch name = U-FD7

#Net "UsbClk" LOC = H2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L41P_GCLK27_M3DQ4, Sch name = U-IFCLK
#Net "UsbDir" LOC = F6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55P_M3A13, Sch name = U-SLCS

#Net "UsbWR" LOC = C1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L83N_VREF, Sch name = U-SLWR
#Net "UsbOE" LOC = H6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49P_M3A7, Sch name = U-SLOE

#Net "UsbAdr<1>" LOC = E3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L50P_M3WE, Sch name = U-FIFOAD1
#Net "UsbAdr<0>" LOC = H5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L49N_M3A2, Sch name = U-FIFOAD0

#Net "UsbPktend" LOC = D3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L54N_M3A11, Sch name = U-PKTEND

#Net "UsbFlag" LOC = F5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L55N_M3A14, Sch name = U-FLAGC
#Net "UsbMode" LOC = F1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48N_M3BA1, Sch name = U-INT0#

## onBoard Cellular RAM, Numonyx StrataFlash and Numonyx Quad Flash
#Net "MemOE" LOC = L18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46N_FOE_B_M1DQ3, Sch name = P30-OE
#Net "MemWR" LOC = M16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47P_FWE_B_M1DQ0, Sch name = P30-WE
#Net "MemAdv" LOC = H18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43N_GCLK4_M1DQ5, Sch name = P30-ADV
#Net "MemWait" LOC = V4 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63N, Sch name = P30-WAIT
#Net "MemClk" LOC = R10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29P_GCLK3, Sch name = P30-CLK

#Net "RamCS" LOC = L15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42P_GCLK7_M1UDM, Sch name = MT-CE
#Net "RamCRE" LOC = M18 |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L47N_LDC_M1DQ1, Sch name = MT-CRE
#Net "RamUB" LOC = K15  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = MT-UB
#Net "RamLB" LOC = K16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L41N_GCLK8_M1CASN, Sch name = MT-LB

#Net "FlashCS" LOC = L17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L46P_FCS_B_M1DQ2, Sch name = P30-CE
#Net "FlashRp" LOC = T4  | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L63P, Sch name = P30-RST

#Net "QuadSpiFlashCS" LOC = V3  | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L65N_CSO_B_2, Sch name = CS
#Net "QuadSpiFlashSck"  LOC = R15 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L1P_CCLK_2, Sch name = SCK

#Net "MemAdr<1>" LOC = K18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45N_A0_M1LDQSN, Sch name = P30-A0
#Net "MemAdr<2>" LOC = K17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L45P_A1_M1LDQS, Sch name = P30-A1
#Net "MemAdr<3>" LOC = J18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44N_A2_M1DQ7, Sch name = P30-A2
#Net "MemAdr<4>" LOC = J16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L44P_A3_M1DQ6, Sch name = P30-A3
#Net "MemAdr<5>" LOC = G18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38N_A4_M1CLKN, Sch name = P30-A4
#Net "MemAdr<6>" LOC = G16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L38P_A5_M1CLK, Sch name = P30-A5
#Net "MemAdr<7>" LOC = H16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37N_A6_M1A1, Sch name = P30-A6
#Net "MemAdr<8>" LOC = H15  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L37P_A7_M1A0, Sch name = P30-A7
#Net "MemAdr<9>" LOC = H14  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36N_A8_M1BA1, Sch name = P30-A8
#Net "MemAdr<10>" LOC = H13  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L36P_A9_M1BA0, Sch name = P30-A9
#Net "MemAdr<11>" LOC = F18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35N_A10_M1A2, Sch name = P30-A10
#Net "MemAdr<12>" LOC = F17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L35P_A11_M1A7, Sch name = P30-A11
#Net "MemAdr<13>" LOC = K13  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34N_A12_M1BA2, Sch name = P30-A12
#Net "MemAdr<14>" LOC = K12  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L34P_A13_M1WE, Sch name = P30-A13
#Net "MemAdr<15>" LOC = E18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33N_A14_M1A4, Sch name = P30-A14
#Net "MemAdr<16>" LOC = E16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L33P_A15_M1A10, Sch name = P30-A15
#Net "MemAdr<17>" LOC = G13  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32N_A16_M1A9, Sch name = P30-A16
#Net "MemAdr<18>" LOC = H12  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L32P_A17_M1A8, Sch name = P30-A17
#Net "MemAdr<19>" LOC = D18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31N_A18_M1A12, Sch name = P30-A18
#Net "MemAdr<20>" LOC = D17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L31P_A19_M1CKE, Sch name = P30-A19
#Net "MemAdr<21>" LOC = G14  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30N_A20_M1A11, Sch name = P30-A20
#Net "MemAdr<22>" LOC = F14  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L30P_A21_M1RESET Sch name = P30-A21
#Net "MemAdr<23>" LOC = C18  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29N_A22_M1A14, Sch name = P30-A22
#Net "MemAdr<24>" LOC = C17  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L29P_A23_M1A13, Sch name = P30-A23
#Net "MemAdr<25>" LOC = F16  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1N_A24_VREF, Sch name = P30-A24
#Net "MemAdr<26>" LOC = F15  |  IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L1P_A25, Sch name = P30-A25

#Net "QuadSpiFlashDB<0>" LOC = T13 |  IOSTANDARD = LVCMOS33; #Dual/Quad SPI Flash DB<0>, Bank = MISC, pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI
#Net "MemDB<0>" LOC = R13 |  IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<0>, or Dual/Quad SPI Flash DB<1>, Bank = MISC, pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = P30-DQ0
#Net "MemDB<1>" LOC = T14 |  IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<1>, or Quad SPI Flash DB<2>, Bank = MISC, pin name = IO_L12P_D1_MISO2_2, Sch name = P30-DQ1
#Net "MemDB<2>" LOC = V14 |  IOSTANDARD = LVCMOS33; #Ram or Numonyx Paralell Flash DB<2>, or Quad SPI Flash DB<3>, Bank = MISC, pin name = IO_L12N_D2_MISO3_2, Sch name = P30-DQ2
#Net "MemDB<3>" LOC = U5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49P_D3, Sch name = P30-DQ3
#Net "MemDB<4>" LOC = V5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_49N_D4, Sch name = P30-DQ4
#Net "MemDB<5>" LOC = R3  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62P_D5, Sch name = P30-DQ5
#Net "MemDB<6>"  LOC = T3  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L62N_D6, Sch name = P30-DQ6
#Net "MemDB<7>"  LOC = R5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L48P_D7, Sch name = P30-DQ7
#Net "MemDB<8>"  LOC = N5  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64P_D8, Sch name = P30-DQ8
#Net "MemDB<9>"  LOC = P6  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L64N_D9, Sch name = P30-DQ9
#Net "MemDB<10>"  LOC = P12 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L13N_D10, Sch name = P30-DQ10
#Net "MemDB<11>"  LOC = U13 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14P_D11, Sch name = P30-DQ11
#Net "MemDB<12>"  LOC = V13 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L14N_D12, Sch name = P30-DQ12
#Net "MemDB<13>"  LOC = U10 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L30P_GCLK1_D13, Sch name = P30-DQ13
#Net "MemDB<14>"  LOC = R8  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31P_GCLK31_D14, Sch name = P30-DQ14
#Net "MemDB<15>"  LOC = T8  |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L31N_GCLK30_D15, Sch name = P30-DQ15

## SMSC ethernet PHY
#Net "PhyRstn" LOC = P3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2N, Sch name = ETH-RST
#Net "PhyCrs" LOC = N3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L1N_VREF, Sch name = ETH-CRS
#Net "PhyCol" LOC = P4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L2P, Sch name = ETH-COL
#Net "PhyClk25Mhz" LOC = N4 | IOSTANDARD = LVCMOS33; #Unconnected if R172 is not loaded, Bank = 3, pin name = IO_L1P, Sch name = ETH-CLK25MHZ

#Net "PhyTxd<3>" LOC = T1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33N_M3DQ13, Sch name = ETH-TXD3 
#Net "PhyTxd<2>" LOC  = T2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L33P_M3DQ12, Sch name = ETH-TXD2
#Net "PhyTxd<1>" LOC = U1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32N_M3DQ15, Sch name = ETH-TXD1
#Net "PhyTxd<0>" LOC = U2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L32P_M3DQ14, Sch name = ETH-TXD0
#Net "PhyTxEn" LOC = L2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37P_M3DQ0, Sch name = ETH-TX_EN
#Net "PhyTxClk" LOC = L5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43P_GCLK23_M3RASN, Sch name = ETH-TX_CLK
#Net "PhyTxEr" LOC = P2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34P_M3UDQS, Sch name = ETH-TXD4

#Net "PhyRxd<3>" LOC = M3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36P_M3DQ8, Sch name = ETH-RXD3
#Net "PhyRxd<2>" LOC = N1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35N_M3DQ11, Sch name = ETH-RXD2
#Net "PhyRxd<1>" LOC = N2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L35P_M3DQ10, Sch name = ETH-RXD1
#Net "PhyRxd<0>" LOC = P1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L34N_M3UDQSN, Sch name = ETH-RXD0
#Net "PhyRxDv" LOC = L1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L37N_M3DQ1, Sch name = ETH-RX_DV
#Net "PhyRxEr" LOC = M1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L36N_M3DQ9, Sch name = ETH-RXD4
#Net "PhyRxClk" LOC = H4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44P_GCLK21_M3A5, Sch name = ETH-RX_CLK

#Net "PhyMdc" LOC = M5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31N_VREF, Sch name = ETH-MDC
#Net "PhyMdio" LOC = L6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L31P, Sch name = ETH-MDIO

## Pic USB-HID interface
#Net "PS2KeyboardData" LOC = J13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39P_M1A3, Sch name = PIC-SDI1
#Net "PS2KeyboardClk" LOC = L12 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40P_GCLK11_M1A5, Sch name = PIC-SCK1

#NET "PS2MouseData" LOC = K14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L39N_M1ODT, Sch name = PIC-SDO1
#NET "PS2MouseClk" LOC = L13| IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L40N_GCLK10_M1A6, Sch name = PIC-SS1

#Net "PicGpio<0>" LOC = L16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = PIC-GPIO0
#NET "PicGpio<1>" LOC = H17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L43P_GCLK5_M1DQ4, Sch name = PIC-GPIO1

## Usb-RS232 interface
Net "rx" LOC = N17 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48P_HDC_M1DQ8, Sch name = MCU-RX
Net "tx" LOC = N18 | IOSTANDARD=LVCMOS33; #Bank = 1, pin name = IO_L48N_M1DQ9, Sch name = MCU-TX

## 7 segment display
#Net "seg<0>" LOC = T17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51P_M1DQ12, Sch name = CA
#Net "seg<1>" LOC = T18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L51N_M1DQ13, Sch name = CB
#Net "seg<2>" LOC = U17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52P_M1DQ14, Sch name = CC
#Net "seg<3>" LOC = U18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L52N_M1DQ15, Sch name = CD
#Net "seg<4>" LOC = M14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53P, Sch name = CE
#Net "seg<5>" LOC = N14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L53N_VREF, Sch name = CF
#Net "seg<6>" LOC = L14 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61P, Sch name = CG
#Net "seg<7>" LOC = M13 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L61N, Sch name = DP

#Net "an<0>" LOC = N16 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50N_M1UDQSN, Sch name = AN0
#Net "an<1>" LOC = N15 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L50P_M1UDQS, Sch name = AN1
#Net "an<2>" LOC = P18 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49N_M1DQ11, Sch name = AN2
#Net "an<3>" LOC = P17 | IOSTANDARD = LVCMOS33; #Bank = 1, pin name = IO_L49P_M1DQ10, Sch name = AN3

## Leds
Net "led<0>" LOC = U16 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2P_CMPCLK, Sch name = LD0
Net "led<1>" LOC = V16 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L2N_CMPMOSI, Sch name = LD1
Net "led<2>" LOC = U15 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5P, Sch name = LD2
Net "led<3>" LOC = V15 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L5N, Sch name = LD3
Net "led<4>" LOC = M11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15P, Sch name = LD4
Net "led<5>" LOC = N11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L15N, Sch name = LD5
Net "led<6>" LOC = R11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16P, Sch name = LD6
Net "led<7>" LOC = T11 |  IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L16N_VREF, Sch name = LD7

## Switches
#Net "sw<0>" LOC = T10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L29N_GCLK2, Sch name = SW0
#Net "sw<1>" LOC = T9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32P_GCLK29, Sch name = SW1
#Net "sw<2>" LOC = V9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L32N_GCLK28, Sch name = SW2
#Net "sw<3>" LOC = M8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40P, Sch name = SW3
#Net "sw<4>" LOC = N8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L40N, Sch name = SW4
#Net "sw<5>" LOC = U8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41P, Sch name = SW5
#Net "sw<6>" LOC = V8 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L41N_VREF, Sch name = SW6
#Net "sw<7>" LOC = T5 | IOSTANDARD = LVCMOS33; #Bank = MISC, pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW7

## Buttons
#Net "zapis_fifo" LOC = B8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33P, Sch name = BTNS
Net "reset" LOC = A8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L33N, Sch name = BTNU
Net "btn<0>" LOC = C4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L1N_VREF, Sch name = BTNL
#Net "wysw2_btn" LOC = C9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L34N_GCLK18, Sch name = BTND
#Net "btnr" LOC = D9 | IOSTANDARD = LVCMOS33; # Bank = 0, pin name = IO_L34P_GCLK19, Sch name = BTNR

## VGA Connector
#NET "vgaRed<0> LOC = U7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43P, Sch name = RED0
#NET "vgaRed<1> LOC = V7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L43N, Sch name = RED1
#NET vgaRed<2> LOC = N7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44P, Sch name = RED2
#NET vgaGreen<0> LOC = P8 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L44N, Sch name = GRN0
#NET vgaGreen<1> LOC = T6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45P, Sch name = GRN1
#NET vgaGreen<2> LOC = V6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L45N, Sch name = GRN2
#NET vgaBlue<1> LOC = R7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46P, Sch name = BLU1
#NET vgaBlue<2> LOC = T7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L46N, Sch name = BLU2

#NET "Hsync" LOC = N6 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47P, Sch name = HSYNC
#NET "Vsync" LOC = P7 | IOSTANDARD = LVCMOS33; # Bank = 2, pin name = IO_L47N, Sch name = VSYNC

## 12 pin connectors

##JA
#Net "JA<0>" LOC = T12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19P, Sch name = JA1
#Net "JA<1>" LOC = V12 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L19N, Sch name = JA2  
#Net "JA<2>" LOC = N10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20P, Sch name = JA3
#Net "JA<3>" LOC = P11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L20N, Sch name = JA4
#Net "JA<4>" LOC = M10 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22P, Sch name = JA7
#Net "JA<5>" LOC = N9 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L22N, Sch name = JA8
#Net "JA<6>" LOC = U11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23P, Sch name = JA9
#Net "JA<7>" LOC = V11 | IOSTANDARD = LVCMOS33; #Bank = 2, pin name = IO_L23N, Sch name = JA10

##JB
Net "sclk" LOC = K2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38P_M3DQ2, Sch name = JB1
Net "mosi" LOC = K1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L38N_M3DQ3, Sch name = JB2
Net "miso" LOC = L4 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39P_M3LDQS, Sch name = JB3
Net "cs" LOC = L3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L39N_M3LDQSN, Sch name = JB4
#Net "JB<4>" LOC = J3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P_M3DQ6, Sch name = JB7
#Net "JB<5>" LOC = J1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N_M3DQ7, Sch name = JB8
#Net "JB<6>" LOC = K3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N_GCLK24_M3LDM, Sch name = JB9
#Net "JB<7>" LOC = K5 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = JB10

##JC
#Net "JC<0>" LOC = H3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L44N_GCLK20_M3A6, Sch name = JC1
#Net "JC<1>" LOC = L7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45P_M3A3, Sch name = JC2
#Net "JC<2>" LOC = K6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L45N_M3ODT, Sch name = JC3
#Net "JC<3>" LOC = G3 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46P_M3CLK, Sch name = JC4
#Net "JC<4>" LOC = G1 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L46N_M3CLKN, Sch name = JC7
#Net "JC<5>" LOC = J7 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P_M3A0, Sch name = JC8
#Net "JC<6>" LOC = J6 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N_M3A1, Sch name = JC9
#Net "JC<7>" LOC = F2 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L48P_M3BA0, Sch name = JC10

##JD, LX16 Die only
#Net "JD<0>" LOC = G11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40P, Sch name = JD1
#Net "JD<1>" LOC = F10 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L40N, Sch name = JD2
#Net "JD<2>" LOC = F11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42P, Sch name = JD3
#Net "JD<3>" LOC = E11 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L42N, Sch name = JD4
#Net "JD<4>" LOC = D12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47P, Sch name = JD7
#Net "JD<5>" LOC = C12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L47N, Sch name = JD8
#Net "JD<6>" LOC = F12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51P, Sch name = JD9
#Net "JD<7>" LOC = E12 | IOSTANDARD = LVCMOS33; #Bank = 3, pin name = IO_L51N, Sch name = JD10

## VHDCI Connector
#Net "EXP-IO_P<0>" LOC = B2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2P, Sch name = EXP_IO1_P
#Net "EXP-IO_N<0>" LOC = A2 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L2N, Sch name = EXP_IO1_N
#Net "EXP-IO_P<1>" LOC = D6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3P, Sch name = EXP_IO2_P
#Net "EXP-IO_N<1>" LOC = C6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L3N, Sch name = EXP_IO2_N
#Net "EXP-IO_P<2>" LOC = B3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4P, Sch name = EXP_IO3_P
#Net "EXP-IO_N<2>" LOC = A3 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L4N, Sch name = EXP_IO3_N
#Net "EXP-IO_P<3>" LOC = B4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5P, Sch name = EXP_IO4_P
#Net "EXP-IO_N<3>" LOC = A4 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L5N, Sch name = EXP_IO4_N
#Net "EXP-IO_P<4>" LOC = C5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6P, Sch name = EXP_IO5_P
#Net "EXP-IO_N<4>" LOC = A5 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L6N, Sch name = EXP_IO5_N
#Net "EXP-IO_P<5>" LOC = B6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8P, Sch name = EXP_IO6_P
#Net "EXP-IO_N<5>" LOC = A6 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L8N_VREF, Sch name = EXP_IO6_N
#Net "EXP-IO_P<6>" LOC = C7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10P, Sch name = EXP_IO7_P
#Net "EXP-IO_N<6>" LOC = A7 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L10N, Sch name = EXP_IO7_N
#Net "EXP-IO_P<7>" LOC = D8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11P, Sch name = EXP_IO8_P
#Net "EXP-IO_N<7>" LOC = C8 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L11N, Sch name = EXP_IO8_N
#Net "EXP-IO_P<8>" LOC = B9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35P_GCLK17, Sch name = EXP_IO9_P
#Net "EXP-IO_N<8>" LOC = A9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L35N_GCLK16, Sch name = EXP_IO9_N
#Net "EXP-IO_P<9>" LOC = D11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36P_GCLK15, Sch name = EXP_IO10_P
#Net "EXP-IO_N<9>" LOC = C11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L36N_GCLK14, Sch name = EXP_IO10_N
#Net "EXP-IO_P<10>" LOC = C10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37P_GCLK13, Sch name = EXP_IO11_P
#Net "EXP-IO_N<10>" LOC = A10 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L37N_GCLK12, Sch name = EXP_IO11_N
#Net "EXP-IO_P<11>" LOC = G9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38P, Sch name = EXP_IO12_P
#Net "EXP-IO_N<11>" LOC = F9 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L38N_VREF, Sch name = EXP_IO12_N
#Net "EXP-IO_P<12>" LOC = B11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39P, Sch name = EXP_IO13_P
#Net "EXP-IO_N<12>" LOC = A11 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L39N, Sch name = EXP_IO13_N
#Net "EXP-IO_P<13>" LOC = B12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41P, Sch name = EXP_IO14_P
#Net "EXP-IO_N<13>" LOC = A12 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L41N, Sch name = EXP_IO14_N
#Net "EXP-IO_P<14>" LOC = C13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50P, Sch name = EXP_IO15_P
#Net "EXP-IO_N<14>" LOC = A13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L50N, Sch name = EXP_IO15_N
#Net "EXP-IO_P<15>" LOC = B14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62P, Sch name = EXP_IO16_P
#Net "EXP-IO_N<15>" LOC = A14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L62N_VREF, Sch name = EXP_IO16_N
#Net "EXP-IO_P<16>" LOC = F13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63P_SCP7, Sch name = EXP_IO17_P
#Net "EXP-IO_N<16>" LOC = E13 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L63N_SCP6, Sch name = EXP_IO17_N
#Net "EXP-IO_P<17>" LOC = C15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64P_SCP5, Sch name = EXP_IO18_P
#Net "EXP-IO_N<17>" LOC = A15 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L64N_SCP4, Sch name = EXP_IO18_N
#Net "EXP-IO_P<18>" LOC = D14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65P_SCP3, Sch name = EXP_IO19_P
#Net "EXP-IO_N<18>" LOC = C14 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L65N_SCP2, Sch name = EXP_IO19_N
#Net "EXP-IO_P<19>" LOC = B16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66P_SCP1, Sch name = EXP_IO20_P
#Net "EXP-IO_N<19>" LOC = A16 | IOSTANDARD = LVCMOS33; #Bank = 0, pin name = IO_L66N_SCP0, Sch name = EXP_IO20_N

thanks

KlausST · May 13, 2016

Hi,

SPI and UART are different interfaces.

Do you want to talk about UART or SPI?

Klaus

Ananhasaasneh77 · May 13, 2016

i want uart for now ..
i did spi with this code by connecting from pmod connector to spi_slave fpga and i saw the leds..

i did before uart with the same code that used in the code and its works from hyperterminal to fpga and i saw the leds ..

but i dont knw why it doesnt work in this code ..
so please talk about uart

thanks alot..

KlausST · May 13, 2016

Hi,

In case you haven´t done thhis already: Read about UART communication in general. And read about UART implementation in FPGA.

***

Please focus on the task:
It seems there is USB involved. And it seems a PC is involved.

Please show us the chain of data flow you want to achieve.

***
I can´t find any UART communcation settings. Where are they?
Are you sure there is UART code already?

Klaus

Ananhasaasneh77 · May 13, 2016

yeaaa im sure if u want i can post all the codes that i have for this top module

ads-ee · May 13, 2016

What are you trying to do now?

Are you trying to interface to an SD card? That is what the sd_controller is for...to interface with a Secure Digital flash card. It is not a generic SPI master controller.

Why do you keep switching between various SPI implementations? First it was the Opencores SPI, then the picoblaze SPI, now an SD card (SPI) flash interface, what's next?

Why haven't you taken the steps I've laid out already in another thread (namely: DRAW THE DETAILED BLOCK DIAGRAM OF YOUR SYSTEM!) so we know what you are attempting to do.

From what I've been able to tell after your nearly 40 posts on this same subject.

you want to communicate between two computers using hyperterminal on both computers
the hardware you are using will be two Xilinx eval boards
the link between the PCs and the eval boards will be through UARTs
the link between the eval boards is SPI
you can get SPI only or UART only working, but not both (Why? you never explain how you've hooked all of this up)
you don't like to answer a direct question or nor do you like to accept advice on how to approach this design (given the number members that have given advice you've probably had over 100 years of combined design experience give you suggestions).
you always post information that has nothing to do with the problem you are having (e.g. A UART problem but sd_controller code?????)
you think it's a ucf problem or a SPI code problem (it's not)

I think the real problem here is you don't understand how to connect the UART to the SPI, because you don't understand that you have to design the system first before coding and building a bit file. You also need to use a simulator to verify the functionality of the code before running it through the tools and creating a bit file.

Your entire problem is lack of a structured approach to the problem and a lack of focus on making individual pieces work before adding more stuff (divide and conquer as the saying goes). I don't know what your background is but it's certainly hasn't given you the critical thinking skills you need to analyze code you find and determine how to modify and integrate it into a new design. This is something that you need to develop if you plan on doing any kind of development.

- - - Updated - - -

If I seem a bit harsh, it's not because I'm trying to make you feel bad, it's because I haven't seen anything posted by you that is even remotely useful to help you solve any problem...Hell, I can't even tell what or where your problem is right now!

I honestly believe you aren't capable of doing this project, without a mentor (one that is physically local to you and is NOT accessed via the internet) that you can sit down with and show them what you are doing and can have a conversation with.

- - - Updated - - -

KlausST said:
I can´t find any UART communcation settings. Where are they?
Are you sure there is UART code already?

You won't find any because the code posted has nothing to do with UARTs

Ananhasaasneh77 · May 13, 2016

this what i want..!! and sryy for bothering u guys .. see ya

ads-ee · May 13, 2016

This looks like something you downloaded from the internet?

You have been describing a PC through UART (on eval board) to SPI master through PMOD (eval board) to PMOD (eval board) to SPI slave to UART to anther PC. This drawing shows SPI master connected to a bunch of SPI peripherals.

I give up, until I see something that indicates you are making more of an effort to supply useful information so we can help you, I will stop bothering you with my advice.

Welcome to EDAboard.com

uart with sd controller

Ananhasaasneh77

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KlausST

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