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NCO IP tool altera vhdl(phi_inc_i)

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Kosyas41

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Hello,
I need help with NCO ip tool,vhdl code generated from quartus IP tool,and im trying to add this code in my project. could you please say,what should i put on phi_inc_i?

HTML: 
U_cord_gen : entity work.cord_gen
		port map (

			clk            =>  clk,
			reset_n	=>  not tx_reset,
			clken		=>  clken,
			phi_inc_i	=> phi_inc_i,
			fsin_o =>fsin_o,
			fcos_o =>fcos_o,
			out_valid => tx_sample_raw_valid

		) ;

	 tx_sample_raw_q <= signed(fsin_o);
	 tx_sample_raw_i <= signed(fcos_o);
	 clk <= clk;
	 clken <= tx_enable;
	 phi_inc_i <= "0110110110110111";
clock rate 700MHz
desiired output freq 300 Mhz
phase increment value 28087
Dither level 4
phase accumulator precision 16 bits
angular resolution 16 bits
magnitude resolution 16 bits
 

The phi_inc_i value you set will generate 300 MHz, presumed clken is permanently '1'.

I guess you have calculated phi_inc_I according to the documentation, so what's the actual question?

My question would be if your FPGA supports 700 MHz core clock and if the design achieves timing closure?
 

my fpga cyclone IV.yes i calculated phi_inc_i according to the documentation.The question was about I am correctly defined phi_inc_i in vhdl or I should do it in another way?
 

The data I found shows the C-IV maxes out at 500MHz on the high end part. It might be possible to do 2 samples/cycle @ 350MHz, 3 samples/cycle @ 233Mhz, or 4 samples/cycle @ 175Mhz.
 

So you mean that,with parameters which I mentioned above are not valid for my FPGA?
 

So you mean that,with parameters which I mentioned above are not valid for my FPGA?
Click to expand...
You'll easily find out by compiling the design in Quartus.

Apart from FPGA speed issues, I wonder which DAC supports 700 MHz data rate and 16 Bit resolution?
 


I remember that I designed a system with 16 Bit/500 MSPs 10 years ago, using 16 LVDS links.

But I guess, the OP didn't yet think about the hardware challenges of his design.
 

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