Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[moved] full verilog code for transmitter module, channel module and reciever module

Status
Not open for further replies.
S

sabah8

Newbie level 4
Joined
May 8, 2016
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
79
[moved]full verilog code for transmitter module , channel module and reciever module

HI

i tried to write this code but i was not successful , first i tried to write a top module consists of 3 modules (transmitter,channel,reciever) , my 7-bit data would passed from a channel , i consider 3-bit for parity check and i assumed only the 7-bit data would be changed (because of channel affect ), i applied it by this way : $random | [9:3]data_chk
[9:0]data_chk // i merged data with 3-bit parity check : [9:3]data and [2:0]chk


Since I could not do anything so I need your help
thanks
 

Re: [moved]full verilog code for transmitter module , channel module and reciever mo

It's highly unlikely that you will get anyone to give you code. This is not a file sharing site.

If you post the code (using the appropriate syntax tags) that "was not successful" and ask for help in making that code successful, you will likely get more help than begging forum members to give you code. As the members that answer questions are all volunteers, asking them to do your work for you is considered in poor taste.

If you are desperate for FREE code then go to Opencores and find something there. (FYI most of the code there is poorly written rubbish)
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top