How can i write a testbench and monitor all the AXI4 bus signals in vivado ??

How can i write testbench and monitor all the AXI4 bus signals in vivado ??

I created a simple block design in vivado . it is just a axi4 system having a microblaze, a DDR3 module and a UART-lite. i generated a bit file for this and programmed on vc707 and verified "hello world" program in SDK and mwr and mrd instructions in xsdb console.

my question is , how can i write a testbench and simulate it , so that i can see all axi4 bus signals i.e i want to indirectly figure out the axi4 protocol from those wave forms. please don't say about BFM, i don't have a licence for that.

i am very new to this, if possible provide me the testbench.

Re: How can i write testbench and monitor all the AXI4 bus signals in vivado ??

Write a very simple C code that will write data to the DDR3 module (assuming that it is connected via an AXI interface). You will need SDK and eventually there will be an ELF file generated for the uBlaze. You need to associate this ELF with the uBlaze. For the test-bench you just need to provide clock and reset signals to the top-module.

The above elf should be sufficient to generate AXI bus transactions after reset which you can view in the waveform window.

i am very new to this, if possible provide me the testbench.

Click to expand...

It is very simple and easy....give it a try.

- - - Updated - - -

If u r using an AXI UART then just writing a Hello World and associating the ELF file will suffice. Just provide clk and reset in the TB.

Re: How can i write testbench and monitor all the AXI4 bus signals in vivado ??

ok ! i will try this,
Meanwhile, how come something written in C code inside SDK will reflect in testbench waveform window.
I think, writing a testbench, doing simulation and observing wave window is totally different from dealing with the connected FPGA boad with SDK by writing a c code . i.e on-board testing with SDK is different from simulation.
Am i correct ...??

Re: How can i write testbench and monitor all the AXI4 bus signals in vivado ??

SDK is only a platform for you to generate an ELF file from your C code.
Imagine the ELF file as instructions for the uBlaze to do something which will reside inside the FPGA BRAM/s. In the test bench when you provide continuous clk and after reset, the uBlaze reads those instructions from the BRAM/s and does something. For your case, this something will be either sending out the "Hello World" message via AXI UART or writing something to a DDR3. In both cases, a bus-transaction is generated by the uBlaze. This transaction you can see in simulation.
Using a uBlaze just makes your life easy, having not to write a real test-bench.

If you want to write a "real" test bench, I you need to change your h/w design a bit, i,e the DUT. There are many options, but I will not elaborate on it here.

Hope I am clear!

Re: How can i write testbench and monitor all the AXI4 bus signals in vivado ??

If you plan on running simulations (in say Modelsim) on your uBlaze design. You create a testbench with the uBlaze design, the DDR3, a clock generator and hook both the DDR3 and the clock generator to the DUT (Design Under Test). You mentioned a UART so you'll want to connect that to a BFM (Bus Functional Model) in your testbench that can take the serial output of the DUT and convert it to display messages can be output in the transcript window. You'll probably also want a line in the testbench that can override the default memory file used to initialize the block RAM for the program code.

Not entirely sure how dpaul's "using uBblaze" allows you to not have any testbench, since the uBlaze isn't going to generate a clock for you.

Re: How can i write testbench and monitor all the AXI4 bus signals in vivado ??

Not entirely sure how dpaul's "using uBblaze" allows you to not have any testbench, since the uBlaze isn't going to generate a clock for you.

Click to expand...

It might be that my statement might be a bit misleading.

Using a uBlaze just makes your life easy, having not to write a real test-bench.

Click to expand...

All I wanted to say that if you have a uBlaze driving some modules, then in the test-bench just provide clk and reset to all the modules.