vhdl 2 dimensional array range

I am using ise14.1 vhdl
I have a record

and types


I declared 2 signals


now I want a slice of buffer_7 into buffer_n which is giving array index error when I wrote this line

The signals have different type and aren't assignment compatible. You need to refer to the common base type, using a generate or loop statement.

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2
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what will be happen if I write this


type t_ChargeProperties_stream is array ( 0 to 7) of t_ChargeProperties;
type t_ChargeProperties_stream_n is array ( 0 to 3) of t_ChargeProperties;
type t_ChargeProperties_stream_7 is array ( 0 to 8, 0 to 7 ) of t_ChargeProperties_;

you may get away with this because the slice you created and buffer_n are similar types, so you should be able to do it via a type conversion:

buffer_n <=t_ChargeProperties_stream_n ( buffer_7(0)(0 to 3) );

The slice itself is a different type from buffer_n - hence the need for a type conversion.

Your second attempt is going to fail, as you cannot slice a 2D array at all.

rourabpaul said:

type t_ChargeProperties_stream is array ( 0 to 7) of t_ChargeProperties;
type t_ChargeProperties_stream_n is array ( 0 to 3) of t_ChargeProperties;
type t_ChargeProperties_stream_7 is array ( 0 to 8, 0 to 7 ) of t_ChargeProperties_;

Click to expand...

You should define the type as an unconstrained array like this...
That way you don't need the 'stream_n' or the 'stream_7' versions. You just declare signals of that type and whatever range you want. You'll still need to define the 2D version as a new type, but I would do it like this...
There is no way to take a slice of a 2d array without writing your own function to do so. If you are intent on using slices, then you need to redefine your 2d array type to be an array of an array like this...
Note that when you choose to do it this way as an array of an array rather than a 2d array, the outermost range can be left unconstrained, but the innermost range must be defined as I've shown. I think this might have changed with VHDL-2008 though, don't recall for sure.

Hope that helps.

Kevin Jennings

K-J said:

I think this might have changed with VHDL-2008 though, don't recall for sure.

Click to expand...

Yes it has: